Commit eed2d8e8 authored by Alexander Stein's avatar Alexander Stein Committed by Shawn Guo
Browse files

arm64: dts: imx8-ss-vpu: Fix imx8qm VPU IRQs 



imx8-ss-vpu only contained imx8qxp IRQ numbers, only mu2_m0 uses the
correct imx8qm IRQ number, as imx8qxp lacks this MU.
Fix this by providing imx8qm IRQ numbers in the main imx8-ss-vpu.dtsi
and override the IRQ numbers in SoC-specific imx8qxp-ss-vpu.dtsi, similar
to reg property for VPU core devices.

Fixes: 0d9968d9 ("arm64: dts: freescale: imx8q: add imx vpu codec entries")
Signed-off-by: default avatarAlexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 9852d85e

arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ vpu: vpu@2c000000 { 
	mu_m0: mailbox@2d000000 {

		compatible = "fsl,imx6sx-mu";

		reg = <0x2d000000 0x20000>;

		interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;

		#mbox-cells = <2>;

		power-domains = <&pd IMX_SC_R_VPU_MU_0>;

		status = "disabled";
@@ -24,7 +24,7 @@ mu_m0: mailbox@2d000000 { 
	mu1_m0: mailbox@2d020000 {

		compatible = "fsl,imx6sx-mu";

		reg = <0x2d020000 0x20000>;

		interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;

		interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;

		#mbox-cells = <2>;

		power-domains = <&pd IMX_SC_R_VPU_MU_1>;

		status = "disabled";

arch/arm64/boot/dts/freescale/imx8qxp-ss-vpu.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -5,6 +5,14 @@ 
 * Author: Alexander Stein

 */



&mu_m0 {

	interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;

};



&mu1_m0 {

	interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;

};



&vpu_core0 {

	reg = <0x2d040000 0x10000>;

};