Commit eed9b142 authored by Oliver Upton's avatar Oliver Upton
Browse files

Documentation: KVM: arm64: Describe VGICv3 registers writable pre-init 



KVM allows userspace to control GICD_IIDR.Revision and
GICD_TYPER2.nASSGIcap prior to initialization for the sake of
provisioning the guest-visible feature set. Document the userspace
expectations surrounding accesses to these registers.

Reviewed-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20250724062805.2658919-7-oliver.upton@linux.dev


Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
parent 15b5964a

Documentation/virt/kvm/devices/arm-vgic-v3.rst

+17 −0
Original line number Diff line number Diff line
@@ -78,6 +78,8 @@ Groups: 
    -ENXIO   The group or attribute is unknown/unsupported for this device

             or hardware support is missing.

    -EFAULT  Invalid user pointer for attr->addr.

    -EBUSY   Attempt to write a register that is read-only after

             initialization

    =======  =============================================================
@@ -120,6 +122,15 @@ Groups: 
    Note that distributor fields are not banked, but return the same value

    regardless of the mpidr used to access the register.



    Userspace is allowed to write the following register fields prior to

    initialization of the VGIC:



      =====================

      GICD_IIDR.Revision

      GICD_TYPER2.nASSGIcap

      =====================





    GICD_IIDR.Revision is updated when the KVM implementation is changed in a

    way directly observable by the guest or userspace.  Userspace should read

    GICD_IIDR from KVM and write back the read value to confirm its expected
@@ -128,6 +139,12 @@ Groups: 
    behavior.





    GICD_TYPER2.nASSGIcap allows userspace to control the support of SGIs

    without an active state. At VGIC creation the field resets to the

    maximum capability of the system. Userspace is expected to read the field

    to determine the supported value(s) before writing to the field.





    The GICD_STATUSR and GICR_STATUSR registers are architecturally defined such

    that a write of a clear bit has no effect, whereas a write with a set bit

    clears that value.  To allow userspace to freely set the values of these two