Commit ef0ae098 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'qcom-clk-for-6.11' of... 

Merge tag 'qcom-clk-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-qcom

Pull Qualcomm clk driver updates from Bjorn Andersson:

 - Add clk drivers for Qualcomm SM7150 camera, display and video
 - Add Qualcomm QCM2290 GPU clk driver
 - Add Qualcomm QCS8386/QCS8084 NSS clk driver
 - Add Qualcomm SM8650 camera and video drivers
 - Make qcom_cc_really_probe() take a struct device to allow reuse in
   non-platform-drivers
 - Introduce prepare-only branch clock ops in the qcom clk driver to
   support clocks on buses that take locks
 - Describe parent/child relationship for Qualcomm SC7280 camera GDSCs
 - Support Qualcomm Huayra 2290 alpha PLL
 - Adjust the highest SDCC clock frequency on Qualcomm IPQ6018 to match
   HS200 support
 - Add missing PCIe PIPE clocks on Qualcomm IPQ9574
 - Fix various configurations and properties in the Qualcomm SA8775P,
   X1E80100 and SM7280 drivers
 - Park Qualcomm SM8350 GPU RCGs on XO while disabled
 - Remove unused CONFIG_QCOM_RPMCC Kconfig symbol
 - Add missing MODULE_DESCRIPTIONs to some qcom clk drivers

* tag 'qcom-clk-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (61 commits)
  clk: qcom: gcc-x1e80100: Fix halt_check for all pipe clocks
  clk: qcom: gcc-ipq6018: update sdcc max clock frequency
  clk: qcom: camcc-sm8650: Add SM8650 camera clock controller driver
  dt-bindings: clock: qcom: Add SM8650 camera clock controller
  dt-bindings: clock: qcom: Update the order of SC8280XP camcc header
  clk: qcom: videocc-sm8550: Add SM8650 video clock controller
  clk: qcom: videocc-sm8550: Add support for videocc XO clk ares
  dt-bindings: clock: qcom: Add SM8650 video clock controller
  dt-bindings: clock: qcom: Update SM8450 videocc header file name
  clk: qcom: gpucc-sa8775p: Update wait_val fields for GPU GDSC's
  clk: qcom: gpucc-sa8775p: Park RCG's clk source at XO during disable
  clk: qcom: gpucc-sa8775p: Remove the CLK_IS_CRITICAL and ALWAYS_ON flags
  clk: qcom: gcc-sa8775p: Set FORCE_MEM_CORE_ON for gcc_ufs_phy_ice_core_clk
  clk: qcom: gcc-sa8775p: Update the GDSC wait_val fields and flags
  clk: qcom: gcc-sa8775p: Remove support for UFS hw ctl clocks
  clk: qcom: gpucc-sm8350: Park RCG's clk source at XO during disable
  clk: qcom: nsscc-qca8k: Fix the MDIO functions undefined issue
  clk: qcom: select right config in CLK_QCM2290_GPUCC definition
  clk: qcom: Remove QCOM_RPMCC symbol
  clk: qcom: Add QCM2290 GPU clock controller driver
  ...
parents 1613e604 f27e42c7

Documentation/devicetree/bindings/clock/qcom,dispcc-sc8280xp.yaml

+4 −16
Original line number Diff line number Diff line
@@ -40,31 +40,19 @@ properties: 
      - description: DSI 1 PLL byte clock

      - description: DSI 1 PLL DSI clock



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



  reg:

    maxItems: 1



  power-domains:

    items:

      - description: MMCX power domain



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false

allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

Documentation/devicetree/bindings/clock/qcom,dispcc-sm6350.yaml

+4 −16
Original line number Diff line number Diff line
@@ -37,28 +37,16 @@ properties: 
      - const: dp_phy_pll_link_clk

      - const: dp_phy_pll_vco_div_clk



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



  reg:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false

allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml

+30 −16
Original line number Diff line number Diff line
@@ -27,6 +27,7 @@ properties: 
      - qcom,sm8350-dispcc



  clocks:

    minItems: 7

    items:

      - description: Board XO source

      - description: Byte clock from DSI PHY0
@@ -35,8 +36,15 @@ properties: 
      - description: Pixel clock from DSI PHY1

      - description: Link clock from DP PHY

      - description: VCO DIV clock from DP PHY

      - description: Link clock from eDP PHY

      - description: VCO DIV clock from eDP PHY

      - description: Link clock from DP1 PHY

      - description: VCO DIV clock from DP1 PHY

      - description: Link clock from DP2 PHY

      - description: VCO DIV clock from DP2 PHY



  clock-names:

    minItems: 7

    items:

      - const: bi_tcxo

      - const: dsi0_phy_pll_out_byteclk
@@ -45,18 +53,12 @@ properties: 
      - const: dsi1_phy_pll_out_dsiclk

      - const: dp_phy_pll_link_clk

      - const: dp_phy_pll_vco_div_clk



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



  reg:

    maxItems: 1

      - const: edp_phy_pll_link_clk

      - const: edp_phy_pll_vco_div_clk

      - const: dptx1_phy_pll_link_clk

      - const: dptx1_phy_pll_vco_div_clk

      - const: dptx2_phy_pll_link_clk

      - const: dptx2_phy_pll_vco_div_clk



  power-domains:

    description:
@@ -70,14 +72,26 @@ properties: 


required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false

allOf:

  - $ref: qcom,gcc.yaml#

  - if:

      not:

        properties:

          compatible:

            contains:

              const: qcom,sc8180x-dispcc

    then:

      properties:

        clocks:

          maxItems: 7

        clock-names:

          maxItems: 7



unevaluatedProperties: false



examples:

  - |

Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml

+2 −1
Original line number Diff line number Diff line
@@ -69,6 +69,8 @@ properties: 
    const: 1

    deprecated: true



  '#power-domain-cells': false



required:

  - compatible
@@ -81,7 +83,6 @@ examples: 
      reg = <0x00900000 0x4000>;

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;



      thermal-sensor {

        compatible = "qcom,msm8960-tsens";

Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml

+1 −0
Original line number Diff line number Diff line
@@ -51,6 +51,7 @@ properties: 


required:

  - compatible

  - '#power-domain-cells'



unevaluatedProperties: false