Commit ef224dd2 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
Browse files

clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validation 



Update the clock enable/disable logic to follow the latest hardware
manual's guidelines, ensuring that both CLK_ON and CLK_MON bits are used
to confirm the clock state.

According to the manual, enabling a clock requires setting the
CPG_CLK_ON bit and verifying the clock has started using the CPG_CLK_MON
bit.  Similarly, disabling a clock requires clearing the CPG_CLK_ON bit
and confirming the clock has stopped via the CPG_CLK_MON bit.

Modify `rzv2h_mod_clock_is_enabled()` to check CLK_MON first and then
validate CLK_ON for a more accurate clock status evaluation.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250407165202.197570-6-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent e6c2b4ed

drivers/clk/renesas/rzv2h-cpg.c

+6 −3
Original line number Diff line number Diff line
@@ -573,10 +573,13 @@ static int rzv2h_mod_clock_is_enabled(struct clk_hw *hw) 
	if (clock->mon_index >= 0) {

		offset = GET_CLK_MON_OFFSET(clock->mon_index);

		bitmask = BIT(clock->mon_bit);

	} else {



		if (!(readl(priv->base + offset) & bitmask))

			return 0;

	}



	offset = GET_CLK_ON_OFFSET(clock->on_index);

	bitmask = BIT(clock->on_bit);

	}



	return readl(priv->base + offset) & bitmask;

}