Commit ef2bd6c9 authored by Danila Tikhonov's avatar Danila Tikhonov Committed by Vinod Koul
Browse files

phy: qcom-qmp-ufs: Add SM8475 support 



Add the tables and constants for init sequences for UFS QMP phy found in
SM8475 SoC.

Signed-off-by: default avatarDanila Tikhonov <danila@jiaxyga.com>
Link: https://lore.kernel.org/r/20240327180642.20146-3-danila@jiaxyga.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 5787731c

drivers/phy/qualcomm/phy-qcom-qmp-ufs.c

+71 −0
Original line number Diff line number Diff line
@@ -722,6 +722,38 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = { 
	QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),

};



static const struct qmp_phy_init_tbl sm8475_ufsphy_serdes[] = {

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x18),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0c),

};



static const struct qmp_phy_init_tbl sm8475_ufsphy_g4_serdes[] = {

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x98),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x18),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x32),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0f),

};



static const struct qmp_phy_init_tbl sm8475_ufsphy_g4_pcs[] = {

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x0b),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04),

	QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04),

};



static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = {

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9),

	QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
@@ -1346,6 +1378,42 @@ static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { 
	.regs			= ufsphy_v5_regs_layout,

};



static const struct qmp_phy_cfg sm8475_ufsphy_cfg = {

	.lanes			= 2,



	.offsets		= &qmp_ufs_offsets_v6,

	.max_supported_gear	= UFS_HS_G4,



	.tbls = {

		.serdes		= sm8475_ufsphy_serdes,

		.serdes_num	= ARRAY_SIZE(sm8475_ufsphy_serdes),

		.tx		= sm8550_ufsphy_tx,

		.tx_num		= ARRAY_SIZE(sm8550_ufsphy_tx),

		.rx		= sm8550_ufsphy_rx,

		.rx_num		= ARRAY_SIZE(sm8550_ufsphy_rx),

		.pcs		= sm8550_ufsphy_pcs,

		.pcs_num	= ARRAY_SIZE(sm8550_ufsphy_pcs),

	},

	.tbls_hs_b = {

		.serdes		= sm8550_ufsphy_hs_b_serdes,

		.serdes_num	= ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes),

	},

	.tbls_hs_overlay[0] = {

		.serdes		= sm8475_ufsphy_g4_serdes,

		.serdes_num	= ARRAY_SIZE(sm8475_ufsphy_g4_serdes),

		.tx		= sm8550_ufsphy_g4_tx,

		.tx_num		= ARRAY_SIZE(sm8550_ufsphy_g4_tx),

		.rx		= sm8550_ufsphy_g4_rx,

		.rx_num		= ARRAY_SIZE(sm8550_ufsphy_g4_rx),

		.pcs		= sm8475_ufsphy_g4_pcs,

		.pcs_num	= ARRAY_SIZE(sm8475_ufsphy_g4_pcs),

		.max_gear	= UFS_HS_G4,

	},

	.vreg_list		= qmp_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),

	.regs			= ufsphy_v6_regs_layout,

};



static const struct qmp_phy_cfg sm8550_ufsphy_cfg = {

	.lanes			= 2,
@@ -1941,6 +2009,9 @@ static const struct of_device_id qmp_ufs_of_match_table[] = { 
	}, {

		.compatible = "qcom,sm8450-qmp-ufs-phy",

		.data = &sm8450_ufsphy_cfg,

	}, {

		.compatible = "qcom,sm8475-qmp-ufs-phy",

		.data = &sm8475_ufsphy_cfg,

	}, {

		.compatible = "qcom,sm8550-qmp-ufs-phy",

		.data = &sm8550_ufsphy_cfg,