Commit ef58e0ad authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dpu: get INTF blocks directly rather than through RM 



INTF blocks are not really handled by resource manager, they are
assigned at dpu_encoder_setup_display using dpu_encoder_get_intf().
Then this allocation is passed to RM and then returned to then
dpu_encoder.
So allocate them outside of RM and use them directly.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Link: https://lore.kernel.org/r/20220121210618.3482550-4-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent d5c5e78f

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

+3 −33
Original line number Diff line number Diff line
@@ -420,26 +420,6 @@ int dpu_encoder_get_linecount(struct drm_encoder *drm_enc) 
	return linecount;

}



void dpu_encoder_get_hw_resources(struct drm_encoder *drm_enc,

				  struct dpu_encoder_hw_resources *hw_res)

{

	struct dpu_encoder_virt *dpu_enc = NULL;

	int i = 0;



	dpu_enc = to_dpu_encoder_virt(drm_enc);

	DPU_DEBUG_ENC(dpu_enc, "\n");



	/* Query resources used by phys encs, expected to be without overlap */

	memset(hw_res, 0, sizeof(*hw_res));



	for (i = 0; i < dpu_enc->num_phys_encs; i++) {

		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];



		if (phys->ops.get_hw_resources)

			phys->ops.get_hw_resources(phys, hw_res);

	}

}



static void dpu_encoder_destroy(struct drm_encoder *drm_enc)

{

	struct dpu_encoder_virt *dpu_enc = NULL;
@@ -973,7 +953,7 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, 
	struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];

	struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };

	int num_lm, num_ctl, num_pp;

	int i, j;

	int i;



	if (!drm_enc) {

		DPU_ERROR("invalid encoder\n");
@@ -1040,8 +1020,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, 
	cstate->num_mixers = num_lm;



	for (i = 0; i < dpu_enc->num_phys_encs; i++) {

		int num_blk;

		struct dpu_hw_blk *hw_blk[MAX_CHANNELS_PER_ENC];

		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];



		if (!dpu_enc->hw_pp[i]) {
@@ -1059,16 +1037,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc, 
		phys->hw_pp = dpu_enc->hw_pp[i];

		phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]);



		num_blk = dpu_rm_get_assigned_resources(&dpu_kms->rm,

			global_state, drm_enc->base.id, DPU_HW_BLK_INTF,

			hw_blk, ARRAY_SIZE(hw_blk));

		for (j = 0; j < num_blk; j++) {

			struct dpu_hw_intf *hw_intf;



			hw_intf = to_dpu_hw_intf(hw_blk[i]);

			if (hw_intf->idx == phys->intf_idx)

				phys->hw_intf = hw_intf;

		}

		if (phys->intf_idx >= INTF_0 && phys->intf_idx < INTF_MAX)

			phys->hw_intf = dpu_rm_get_intf(&dpu_kms->rm, phys->intf_idx);



		if (!phys->hw_intf) {

			DPU_ERROR_ENC(dpu_enc,

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h

+0 −16
Original line number Diff line number Diff line
@@ -18,22 +18,6 @@ 


#define IDLE_TIMEOUT	(66 - 16/2)



/**

 * Encoder functions and data types

 * @intfs:	Interfaces this encoder is using, INTF_MODE_NONE if unused

 */

struct dpu_encoder_hw_resources {

	enum dpu_intf_mode intfs[INTF_MAX];

};



/**

 * dpu_encoder_get_hw_resources - Populate table of required hardware resources

 * @encoder:	encoder pointer

 * @hw_res:	resource table to populate with encoder required resources

 */

void dpu_encoder_get_hw_resources(struct drm_encoder *encoder,

				  struct dpu_encoder_hw_resources *hw_res);



/**

 * dpu_encoder_assign_crtc - Link the encoder to the crtc it's assigned to

 * @encoder:	encoder pointer

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h

+0 −5
Original line number Diff line number Diff line
@@ -91,9 +91,6 @@ struct dpu_encoder_virt_ops { 
 * @disable:			DRM Call. Disable mode.

 * @atomic_check:		DRM Call. Atomic check new DRM state.

 * @destroy:			DRM Call. Destroy and release resources.

 * @get_hw_resources:		Populate the structure with the hardware

 *				resources that this phys_enc is using.

 *				Expect no overlap between phys_encs.

 * @control_vblank_irq		Register/Deregister for VBLANK IRQ

 * @wait_for_commit_done:	Wait for hardware to have flushed the

 *				current pending frames to hardware
@@ -129,8 +126,6 @@ struct dpu_encoder_phys_ops { 
			    struct drm_crtc_state *crtc_state,

			    struct drm_connector_state *conn_state);

	void (*destroy)(struct dpu_encoder_phys *encoder);

	void (*get_hw_resources)(struct dpu_encoder_phys *encoder,

				 struct dpu_encoder_hw_resources *hw_res);

	int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable);

	int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc);

	int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc);

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c

+0 −8
Original line number Diff line number Diff line
@@ -534,13 +534,6 @@ static void dpu_encoder_phys_cmd_destroy(struct dpu_encoder_phys *phys_enc) 
	kfree(cmd_enc);

}



static void dpu_encoder_phys_cmd_get_hw_resources(

		struct dpu_encoder_phys *phys_enc,

		struct dpu_encoder_hw_resources *hw_res)

{

	hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_CMD;

}



static void dpu_encoder_phys_cmd_prepare_for_kickoff(

		struct dpu_encoder_phys *phys_enc)

{
@@ -736,7 +729,6 @@ static void dpu_encoder_phys_cmd_init_ops( 
	ops->enable = dpu_encoder_phys_cmd_enable;

	ops->disable = dpu_encoder_phys_cmd_disable;

	ops->destroy = dpu_encoder_phys_cmd_destroy;

	ops->get_hw_resources = dpu_encoder_phys_cmd_get_hw_resources;

	ops->control_vblank_irq = dpu_encoder_phys_cmd_control_vblank_irq;

	ops->wait_for_commit_done = dpu_encoder_phys_cmd_wait_for_commit_done;

	ops->prepare_for_kickoff = dpu_encoder_phys_cmd_prepare_for_kickoff;

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c

+0 −8
Original line number Diff line number Diff line
@@ -465,13 +465,6 @@ static void dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys *phys_enc) 
	kfree(phys_enc);

}



static void dpu_encoder_phys_vid_get_hw_resources(

		struct dpu_encoder_phys *phys_enc,

		struct dpu_encoder_hw_resources *hw_res)

{

	hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO;

}



static int dpu_encoder_phys_vid_wait_for_vblank(

		struct dpu_encoder_phys *phys_enc)

{
@@ -680,7 +673,6 @@ static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) 
	ops->enable = dpu_encoder_phys_vid_enable;

	ops->disable = dpu_encoder_phys_vid_disable;

	ops->destroy = dpu_encoder_phys_vid_destroy;

	ops->get_hw_resources = dpu_encoder_phys_vid_get_hw_resources;

	ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq;

	ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done;

	ops->wait_for_vblank = dpu_encoder_phys_vid_wait_for_vblank;