Commit ef6ee3a3 authored by Heiner Kallweit's avatar Heiner Kallweit Committed by David S. Miller
Browse files

net: phy: add PHY_EEE_CAP2_FEATURES 



As a prerequisite for adding EEE CAP2 register support, complement
PHY_EEE_CAP1_FEATURES with PHY_EEE_CAP2_FEATURES.
For now only 2500baseT and 5000baseT modes are supported.

Signed-off-by: default avatarHeiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 80e4021c

drivers/net/phy/phy_device.c

+11 −0
Original line number Diff line number Diff line
@@ -148,6 +148,14 @@ static const int phy_eee_cap1_features_array[] = { 
__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap1_features) __ro_after_init;

EXPORT_SYMBOL_GPL(phy_eee_cap1_features);



static const int phy_eee_cap2_features_array[] = {

	ETHTOOL_LINK_MODE_2500baseT_Full_BIT,

	ETHTOOL_LINK_MODE_5000baseT_Full_BIT,

};



__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap2_features) __ro_after_init;

EXPORT_SYMBOL_GPL(phy_eee_cap2_features);



static void features_init(void)

{

	/* 10/100 half/full*/
@@ -232,6 +240,9 @@ static void features_init(void) 
	linkmode_set_bit_array(phy_eee_cap1_features_array,

			       ARRAY_SIZE(phy_eee_cap1_features_array),

			       phy_eee_cap1_features);

	linkmode_set_bit_array(phy_eee_cap2_features_array,

			       ARRAY_SIZE(phy_eee_cap2_features_array),

			       phy_eee_cap2_features);



}

include/linux/phy.h

+2 −0
Original line number Diff line number Diff line
@@ -54,6 +54,7 @@ extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_features) __ro_after_init; 
extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_fec_features) __ro_after_init;

extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_10gbit_full_features) __ro_after_init;

extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap1_features) __ro_after_init;

extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap2_features) __ro_after_init;



#define PHY_BASIC_FEATURES ((unsigned long *)&phy_basic_features)

#define PHY_BASIC_T1_FEATURES ((unsigned long *)&phy_basic_t1_features)
@@ -65,6 +66,7 @@ extern __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_eee_cap1_features) __ro_after_init; 
#define PHY_10GBIT_FEC_FEATURES ((unsigned long *)&phy_10gbit_fec_features)

#define PHY_10GBIT_FULL_FEATURES ((unsigned long *)&phy_10gbit_full_features)

#define PHY_EEE_CAP1_FEATURES ((unsigned long *)&phy_eee_cap1_features)

#define PHY_EEE_CAP2_FEATURES ((unsigned long *)&phy_eee_cap2_features)



extern const int phy_basic_ports_array[3];

extern const int phy_fibre_port_array[1];