Commit ef79fafe authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Eliminate intel_dp.regs.dp_tp_{ctl,status} 



Now that we've plumbed the crtc state all the way down we can
eliminate the DP_TP_{CTL,STATUS} register offsets from intel_dp,
and instead we derive them directly from the crtc state.

And thus we can get rid of the nasty hack in intel_ddi_get_config()
which mutates intel_dp during the readout.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200929233449.32323-12-ville.syrjala@linux.intel.com


Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
parent a621860a

drivers/gpu/drm/i915/display/intel_ddi.c

+57 −50
Original line number Diff line number Diff line
@@ -3295,6 +3295,37 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port, 
	}

}



static enum transcoder

tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)

{

	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))

		return crtc_state->mst_master_transcoder;

	else

		return crtc_state->cpu_transcoder;

}



i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,

			 const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);



	if (INTEL_GEN(dev_priv) >= 12)

		return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));

	else

		return DP_TP_CTL(encoder->port);

}



i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,

			    const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);



	if (INTEL_GEN(dev_priv) >= 12)

		return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));

	else

		return DP_TP_STATUS(encoder->port);

}



static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,

					const struct intel_crtc_state *crtc_state)

{
@@ -3319,11 +3350,12 @@ static void intel_ddi_enable_fec(struct intel_encoder *encoder, 
		return;



	intel_dp = enc_to_intel_dp(encoder);

	val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);

	val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));

	val |= DP_TP_CTL_FEC_ENABLE;

	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);

	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);



	if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,

	if (intel_de_wait_for_set(dev_priv,

				  dp_tp_status_reg(encoder, crtc_state),

				  DP_TP_STATUS_FEC_ENABLE_LIVE, 1))

		drm_err(&dev_priv->drm,

			"Timed out waiting for FEC Enable Status\n");
@@ -3340,10 +3372,10 @@ static void intel_ddi_disable_fec_state(struct intel_encoder *encoder, 
		return;



	intel_dp = enc_to_intel_dp(encoder);

	val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);

	val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));

	val &= ~DP_TP_CTL_FEC_ENABLE;

	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);

	intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);

	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);

	intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));

}



static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -3357,15 +3389,11 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, 
	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);

	bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);

	int level = intel_ddi_dp_level(intel_dp);

	enum transcoder transcoder = crtc_state->cpu_transcoder;



	intel_dp_set_link_params(intel_dp,

				 crtc_state->port_clock,

				 crtc_state->lane_count);



	intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);

	intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);



	/*

	 * 1. Enable Power Wells

	 *
@@ -3682,12 +3710,10 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder, 
	}



	if (intel_crtc_has_dp_encoder(crtc_state)) {

		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);



		val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);

		val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));

		val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);

		val |= DP_TP_CTL_LINK_TRAIN_PAT1;

		intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);

		intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);

	}



	/* Disable FEC in DP Sink */
@@ -4184,13 +4210,13 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state, 
static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,

					   const struct intel_crtc_state *crtc_state)

{

	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);

	enum port port = dig_port->base.port;

	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	enum port port = encoder->port;

	u32 dp_tp_ctl, ddi_buf_ctl;

	bool wait = false;



	dp_tp_ctl = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);

	dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));



	if (dp_tp_ctl & DP_TP_CTL_ENABLE) {

		ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
@@ -4202,8 +4228,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 


		dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);

		dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;

		intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);

		intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);

		intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);

		intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));



		if (wait)

			intel_wait_ddi_buf_idle(dev_priv, port);
@@ -4217,8 +4243,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp, 
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))

			dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;

	}

	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);

	intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);

	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);

	intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));



	intel_dp->DP |= DDI_BUF_CTL_ENABLE;

	intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
@@ -4231,11 +4257,12 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 
				     const struct intel_crtc_state *crtc_state,

				     u8 dp_train_pat)

{

	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);

	u32 temp;



	temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);

	temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));



	temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;

	switch (dp_train_pat & train_pat_mask) {
@@ -4256,7 +4283,7 @@ static void intel_ddi_set_link_train(struct intel_dp *intel_dp, 
		break;

	}



	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);

	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp);

}



static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
@@ -4267,10 +4294,10 @@ static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 
	enum port port = encoder->port;

	u32 val;



	val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);

	val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));

	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;

	val |= DP_TP_CTL_LINK_TRAIN_IDLE;

	intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);

	intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);



	/*

	 * Until TGL on PORT_A we can have only eDP in SST mode. There the only
@@ -4282,7 +4309,8 @@ static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp, 
	if (port == PORT_A && INTEL_GEN(dev_priv) < 12)

		return;



	if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,

	if (intel_de_wait_for_set(dev_priv,

				  dp_tp_status_reg(encoder, crtc_state),

				  DP_TP_STATUS_IDLE_DONE, 1))

		drm_err(&dev_priv->drm,

			"Timed out waiting for DP idle patterns\n");
@@ -4380,7 +4408,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder, 
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);

	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;

	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

	u32 temp, flags = 0;



	/* XXX: DSI transcoder paranoia */
@@ -4450,12 +4477,7 @@ void intel_ddi_get_config(struct intel_encoder *encoder, 
		intel_dp_get_m_n(intel_crtc, pipe_config);



		if (INTEL_GEN(dev_priv) >= 11) {

			i915_reg_t dp_tp_ctl;



			if (IS_GEN(dev_priv, 11))

				dp_tp_ctl = DP_TP_CTL(encoder->port);

			else

				dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);

			i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);



			pipe_config->fec_enable =

				intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
@@ -4488,16 +4510,6 @@ void intel_ddi_get_config(struct intel_encoder *encoder, 
		break;

	}



	if (INTEL_GEN(dev_priv) >= 12) {

		enum transcoder transcoder =

			intel_dp_mst_is_slave_trans(pipe_config) ?

			pipe_config->mst_master_transcoder :

			pipe_config->cpu_transcoder;



		intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);

		intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);

	}



	pipe_config->has_audio =

		intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
@@ -4762,11 +4774,6 @@ intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) 
	dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;

	dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;



	if (INTEL_GEN(dev_priv) < 12) {

		dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);

		dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);

	}



	if (!intel_dp_init_connector(dig_port, connector)) {

		kfree(connector);

		return NULL;

drivers/gpu/drm/i915/display/intel_ddi.h

+5 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
#define __INTEL_DDI_H__



#include "intel_display.h"

#include "i915_reg.h"



struct drm_connector_state;

struct drm_i915_private;
@@ -18,6 +19,10 @@ struct intel_dpll_hw_state; 
struct intel_encoder;

enum transcoder;



i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,

			 const struct intel_crtc_state *crtc_state);

i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,

			    const struct intel_crtc_state *crtc_state);

void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,

				struct intel_encoder *intel_encoder,

				const struct intel_crtc_state *old_crtc_state,

drivers/gpu/drm/i915/display/intel_display_types.h

+0 −8
Original line number Diff line number Diff line
@@ -1338,14 +1338,6 @@ struct intel_dp { 
	bool is_mst;

	int active_mst_links;



	/*

	 * DP_TP_* registers may be either on port or transcoder register space.

	 */

	struct {

		i915_reg_t dp_tp_ctl;

		i915_reg_t dp_tp_status;

	} regs;



	/* connector directly attached - won't be use for modeset in mst world */

	struct intel_connector *attached_connector;

drivers/gpu/drm/i915/display/intel_dp.c

+0 −2
Original line number Diff line number Diff line
@@ -8109,8 +8109,6 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, 


	dig_port->dp.output_reg = output_reg;

	dig_port->max_lanes = 4;

	dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);

	dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);



	intel_encoder->type = INTEL_OUTPUT_DP;

	intel_encoder->power_domain = intel_port_to_power_domain(port);

drivers/gpu/drm/i915/display/intel_dp_mst.c

+14 −10
Original line number Diff line number Diff line
@@ -318,19 +318,23 @@ intel_dp_mst_atomic_check(struct drm_connector *connector, 
	return ret;

}



static void clear_act_sent(struct intel_dp *intel_dp)

static void clear_act_sent(struct intel_encoder *encoder,

			   const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *i915 = dp_to_i915(intel_dp);

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);



	intel_de_write(i915, intel_dp->regs.dp_tp_status,

	intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state),

		       DP_TP_STATUS_ACT_SENT);

}



static void wait_for_act_sent(struct intel_dp *intel_dp)

static void wait_for_act_sent(struct intel_encoder *encoder,

			      const struct intel_crtc_state *crtc_state)

{

	struct drm_i915_private *i915 = dp_to_i915(intel_dp);

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);

	struct intel_dp *intel_dp = &intel_mst->primary->dp;



	if (intel_de_wait_for_set(i915, intel_dp->regs.dp_tp_status,

	if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state),

				  DP_TP_STATUS_ACT_SENT, 1))

		drm_err(&i915->drm, "Timed out waiting for ACT sent\n");
@@ -392,7 +396,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, 


	drm_dp_update_payload_part2(&intel_dp->mst_mgr);



	clear_act_sent(intel_dp);

	clear_act_sent(encoder, old_crtc_state);



	val = intel_de_read(dev_priv,

			    TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder));
@@ -401,7 +405,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, 
		       TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder),

		       val);



	wait_for_act_sent(intel_dp);

	wait_for_act_sent(encoder, old_crtc_state);



	drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, connector->port);
@@ -535,7 +539,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, 


	drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);



	clear_act_sent(intel_dp);

	clear_act_sent(encoder, pipe_config);



	intel_ddi_enable_transcoder_func(encoder, pipe_config);
@@ -549,7 +553,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, 
	drm_dbg_kms(&dev_priv->drm, "active links %d\n",

		    intel_dp->active_mst_links);



	wait_for_act_sent(intel_dp);

	wait_for_act_sent(encoder, pipe_config);



	drm_dp_update_payload_part2(&intel_dp->mst_mgr);