Commit ef9256d2 authored by Mike Frysinger's avatar Mike Frysinger Committed by Linus Torvalds
Browse files

Blackfin arch: issue reset via SWRST so we dont clobber the watchdog state 



Signed-off-by: default avatarMike Frysinger <michael.frysinger@analog.com>
Signed-off-by: default avatarBryan Wu <bryan.wu@analog.com>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent c0fc525d

arch/blackfin/mach-bf533/head.S

+16 −52
Original line number Diff line number Diff line
@@ -481,66 +481,30 @@ ENTRY(_bfin_reset) 
	[p0] = r0;

	SSYNC;



	/* Disable the WDOG TIMER */

	p0.h = hi(WDOG_CTL);

	p0.l = lo(WDOG_CTL);

	r0.l = 0xAD6;

	w[p0] = r0.l;

	SSYNC;



	/* Clear the sticky bit incase it is already set */

	p0.h = hi(WDOG_CTL);

	p0.l = lo(WDOG_CTL);

	r0.l = 0x8AD6;

	w[p0] = r0.l;

	/* make sure SYSCR is set to use BMODE */

	P0.h = hi(SYSCR);

	P0.l = lo(SYSCR);

	R0.l = 0x0;

	W[P0] = R0.l;

	SSYNC;



	/* Program the count value */

	R0.l = 0x100;

	R0.h = 0x0;

	P0.h = hi(WDOG_CNT);

	P0.l = lo(WDOG_CNT);

	[P0] = R0;

	/* issue a system soft reset */

	P1.h = hi(SWRST);

	P1.l = lo(SWRST);

	R1.l = 0x0007;

	W[P1] = R1;

	SSYNC;



	/* Program WDOG_STAT if necessary */

	P0.h = hi(WDOG_CTL);

	P0.l = lo(WDOG_CTL);

	R0 = W[P0](Z);

	CC = BITTST(R0,1);

	if !CC JUMP .LWRITESTAT;

	CC = BITTST(R0,2);

	if !CC JUMP .LWRITESTAT;

	JUMP .LSKIP_WRITE;



.LWRITESTAT:

	/* When watch dog timer is enabled, a write to STAT will load the contents of CNT to STAT */

	R0 = 0x0000(z);

	P0.h = hi(WDOG_STAT);

	P0.l = lo(WDOG_STAT)

	[P0] = R0;

	SSYNC;



.LSKIP_WRITE:

	/* Enable the reset event */

	P0.h = hi(WDOG_CTL);

	P0.l = lo(WDOG_CTL);

	R0 = W[P0](Z);

	BITCLR(R0,1);

	BITCLR(R0,2);

	W[P0] = R0.L;

	SSYNC;

	NOP;



	/* Enable the wdog counter */

	R0 = W[P0](Z);

	BITCLR(R0,4);

	W[P0] = R0.L;

	/* clear system soft reset */

	R0.l = 0x0000;

	W[P0] = R0;

	SSYNC;



	IDLE;

	/* issue core reset */

	raise 1;



	RTS;

ENDPROC(_bfin_reset)



#if CONFIG_DEBUG_KERNEL_START

debug_kernel_start_trap:

arch/blackfin/mach-bf537/head.S

+16 −54
Original line number Diff line number Diff line
@@ -517,68 +517,30 @@ _delay_lab1_end: 
	[p0] = r0;

	SSYNC;



	/* Disable the WDOG TIMER */

	p0.h = hi(WDOG_CTL);

	p0.l = lo(WDOG_CTL);

	r0.l = 0xAD6;

	w[p0] = r0.l;

	/* make sure SYSCR is set to use BMODE */

	P0.h = hi(SYSCR);

	P0.l = lo(SYSCR);

	R0.l = 0x0;

	W[P0] = R0.l;

	SSYNC;



	/* Clear the sticky bit incase it is already set */

	p0.h = hi(WDOG_CTL);

	p0.l = lo(WDOG_CTL);

	r0.l = 0x8AD6;

	w[p0] = r0.l;

	/* issue a system soft reset */

	P1.h = hi(SWRST);

	P1.l = lo(SWRST);

	R1.l = 0x0007;

	W[P1] = R1;

	SSYNC;



	/* Program the count value */

	R0.l = 0x100;

	R0.h = 0x0;

	P0.h = hi(WDOG_CNT);

	P0.l = lo(WDOG_CNT);

	[P0] = R0;

	SSYNC;



	/* Program WDOG_STAT if necessary */

	P0.h = hi(WDOG_CTL);

	P0.l = lo(WDOG_CTL);

	R0 = W[P0](Z);

	CC = BITTST(R0,1);

	if !CC JUMP .LWRITESTAT;

	CC = BITTST(R0,2);

	if !CC JUMP .LWRITESTAT;

	JUMP .LSKIP_WRITE;



.LWRITESTAT:

	/* When watch dog timer is enabled,

	 * a write to STAT will load the contents of CNT to STAT

	 */

	R0 = 0x0000(z);

	P0.h = hi(WDOG_STAT);

	P0.l = lo(WDOG_STAT)

	[P0] = R0;

	SSYNC;



.LSKIP_WRITE:

	/* Enable the reset event */

	P0.h = hi(WDOG_CTL);

	P0.l = lo(WDOG_CTL);

	R0 = W[P0](Z);

	BITCLR(R0,1);

	BITCLR(R0,2);

	W[P0] = R0.L;

	SSYNC;

	NOP;



	/* Enable the wdog counter */

	R0 = W[P0](Z);

	BITCLR(R0,4);

	W[P0] = R0.L;

	/* clear system soft reset */

	R0.l = 0x0000;

	W[P0] = R0;

	SSYNC;



	IDLE;

	/* issue core reset */

	raise 1;



	RTS;

ENDPROC(_bfin_reset)



.data

arch/blackfin/mach-bf561/head.S

+16 −54
Original line number Diff line number Diff line
@@ -427,68 +427,30 @@ ENTRY(_bfin_reset) 
	[p0] = r0;

	SSYNC;



	/* Disable the WDOG TIMER */

	p0.h = hi(WDOGA_CTL);

	p0.l = lo(WDOGA_CTL);

	r0.l = 0xAD6;

	w[p0] = r0.l;

	/* make sure SYSCR is set to use BMODE */

	P0.h = hi(SICA_SYSCR);

	P0.l = lo(SICA_SYSCR);

	R0.l = 0x0;

	W[P0] = R0.l;

	SSYNC;



	/* Clear the sticky bit incase it is already set */

	p0.h = hi(WDOGA_CTL);

	p0.l = lo(WDOGA_CTL);

	r0.l = 0x8AD6;

	w[p0] = r0.l;

	SSYNC;



	/* Program the count value */

	R0.l = 0x100;

	R0.h = 0x0;

	P0.h = hi(WDOGA_CNT);

	P0.l = lo(WDOGA_CNT);

	[P0] = R0;

	/* issue a system soft reset */

	P1.h = hi(SICA_SWRST);

	P1.l = lo(SICA_SWRST);

	R1.l = 0x0007;

	W[P1] = R1;

	SSYNC;



	/* Program WDOG_STAT if necessary */

	P0.h = hi(WDOGA_CTL);

	P0.l = lo(WDOGA_CTL);

	R0 = W[P0](Z);

	CC = BITTST(R0,1);

	if !CC JUMP .LWRITESTAT;

	CC = BITTST(R0,2);

	if !CC JUMP .LWRITESTAT;

	JUMP .LSKIP_WRITE;



.LWRITESTAT:

	/* When watch dog timer is enabled,

	 * a write to STAT will load the contents of CNT to STAT

	 */

	R0 = 0x0000(z);

	P0.h = hi(WDOGA_STAT);

	P0.l = lo(WDOGA_STAT)

	[P0] = R0;

	SSYNC;



.LSKIP_WRITE:

	/* Enable the reset event */

	P0.h = hi(WDOGA_CTL);

	P0.l = lo(WDOGA_CTL);

	R0 = W[P0](Z);

	BITCLR(R0,1);

	BITCLR(R0,2);

	W[P0] = R0.L;

	SSYNC;

	NOP;



	/* Enable the wdog counter */

	R0 = W[P0](Z);

	BITCLR(R0,4);

	W[P0] = R0.L;

	/* clear system soft reset */

	R0.l = 0x0000;

	W[P0] = R0;

	SSYNC;



	IDLE;

	/* issue core reset */

	raise 1;



	RTS;

ENDPROC(_bfin_reset)



.data