Commit ef9449f0 authored by Lorenzo Bianconi's avatar Lorenzo Bianconi Committed by Paolo Abeni
Browse files

net: airoha: Generalize airoha_ppe2_is_enabled routine 



Rename airoha_ppe2_is_enabled() in airoha_ppe_is_enabled() and
generalize it in order to check if each PPE module is enabled.
Rely on airoha_ppe_is_enabled routine to properly initialize PPE for
AN7583 SoC since AN7583 does not support PPE2.

Reviewed-by: default avatarSimon Horman <horms@kernel.org>
Signed-off-by: default avatarLorenzo Bianconi <lorenzo@kernel.org>
Link: https://patch.msgid.link/20251017-an7583-eth-support-v3-5-f28319666667@kernel.org


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent 5863b4e0

drivers/net/ethernet/airoha/airoha_eth.c

+21 −11
Original line number Diff line number Diff line
@@ -297,8 +297,11 @@ static void airoha_fe_pse_ports_init(struct airoha_eth *eth) 
	int q;



	all_rsv = airoha_fe_get_pse_all_rsv(eth);

	if (airoha_ppe_is_enabled(eth, 1)) {

		/* hw misses PPE2 oq rsv */

	all_rsv += PSE_RSV_PAGES * pse_port_num_queues[FE_PSE_PORT_PPE2];

		all_rsv += PSE_RSV_PAGES *

			   pse_port_num_queues[FE_PSE_PORT_PPE2];

	}

	airoha_fe_set(eth, REG_FE_PSE_BUF_SET, all_rsv);



	/* CMD1 */
@@ -335,13 +338,17 @@ static void airoha_fe_pse_ports_init(struct airoha_eth *eth) 
	for (q = 4; q < pse_port_num_queues[FE_PSE_PORT_CDM4]; q++)

		airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_CDM4, q,

					 PSE_QUEUE_RSV_PAGES);

	if (airoha_ppe_is_enabled(eth, 1)) {

		/* PPE2 */

		for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_PPE2]; q++) {

			if (q < pse_port_num_queues[FE_PSE_PORT_PPE2] / 2)

			airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, q,

				airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2,

							 q,

							 PSE_QUEUE_RSV_PAGES);

			else

			airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2, q, 0);

				airoha_fe_set_pse_oq_rsv(eth, FE_PSE_PORT_PPE2,

							 q, 0);

		}

	}

	/* GMD4 */

	for (q = 0; q < pse_port_num_queues[FE_PSE_PORT_GDM4]; q++)
@@ -1762,8 +1769,11 @@ static int airoha_dev_init(struct net_device *dev) 
			airhoha_set_gdm2_loopback(port);

		fallthrough;

	case 2:

		if (airoha_ppe_is_enabled(eth, 1)) {

			pse_port = FE_PSE_PORT_PPE2;

			break;

		}

		fallthrough;

	default:

		pse_port = FE_PSE_PORT_PPE1;

		break;

drivers/net/ethernet/airoha/airoha_eth.h

+1 −0
Original line number Diff line number Diff line
@@ -627,6 +627,7 @@ static inline bool airoha_is_7581(struct airoha_eth *eth) 
bool airoha_is_valid_gdm_port(struct airoha_eth *eth,

			      struct airoha_gdm_port *port);



bool airoha_ppe_is_enabled(struct airoha_eth *eth, int index);

void airoha_ppe_check_skb(struct airoha_ppe_dev *dev, struct sk_buff *skb,

			  u16 hash, bool rx_wlan);

int airoha_ppe_setup_tc_block_cb(struct airoha_ppe_dev *dev, void *type_data);

drivers/net/ethernet/airoha/airoha_ppe.c

+10 −7
Original line number Diff line number Diff line
@@ -50,9 +50,12 @@ static int airoha_ppe_get_total_num_stats_entries(struct airoha_ppe *ppe) 
	return num_stats;

}



static bool airoha_ppe2_is_enabled(struct airoha_eth *eth)

bool airoha_ppe_is_enabled(struct airoha_eth *eth, int index)

{

	return airoha_fe_rr(eth, REG_PPE_GLO_CFG(1)) & PPE_GLO_CFG_EN_MASK;

	if (index >= eth->soc->num_ppe)

		return false;



	return airoha_fe_rr(eth, REG_PPE_GLO_CFG(index)) & PPE_GLO_CFG_EN_MASK;

}



static u32 airoha_ppe_get_timestamp(struct airoha_ppe *ppe)
@@ -120,7 +123,7 @@ static void airoha_ppe_hw_init(struct airoha_ppe *ppe) 
						 AIROHA_MAX_MTU));

	}



	if (airoha_ppe2_is_enabled(eth)) {

	if (airoha_ppe_is_enabled(eth, 1)) {

		sram_num_entries = PPE1_SRAM_NUM_ENTRIES;

		sram_num_stats_entries =

			airoha_ppe_get_num_stats_entries(ppe);
@@ -518,7 +521,7 @@ static int airoha_ppe_foe_get_flow_stats_index(struct airoha_ppe *ppe, 
		return ppe_num_stats_entries;



	*index = hash;

	if (airoha_ppe2_is_enabled(ppe->eth) &&

	if (airoha_ppe_is_enabled(ppe->eth, 1) &&

	    hash >= ppe_num_stats_entries)

		*index = *index - PPE_STATS_NUM_ENTRIES;
@@ -613,7 +616,7 @@ airoha_ppe_foe_get_entry_locked(struct airoha_ppe *ppe, u32 hash) 
		u32 val;

		int i;



		ppe2 = airoha_ppe2_is_enabled(ppe->eth) &&

		ppe2 = airoha_ppe_is_enabled(ppe->eth, 1) &&

		       hash >= PPE1_SRAM_NUM_ENTRIES;

		airoha_fe_wr(ppe->eth, REG_PPE_RAM_CTRL(ppe2),

			     FIELD_PREP(PPE_SRAM_CTRL_ENTRY_MASK, hash) |
@@ -691,7 +694,7 @@ static int airoha_ppe_foe_commit_entry(struct airoha_ppe *ppe, 


	if (hash < PPE_SRAM_NUM_ENTRIES) {

		dma_addr_t addr = ppe->foe_dma + hash * sizeof(*hwe);

		bool ppe2 = airoha_ppe2_is_enabled(eth) &&

		bool ppe2 = airoha_ppe_is_enabled(eth, 1) &&

			    hash >= PPE1_SRAM_NUM_ENTRIES;



		err = npu->ops.ppe_foe_commit_entry(npu, addr, sizeof(*hwe),
@@ -1286,7 +1289,7 @@ static int airoha_ppe_flush_sram_entries(struct airoha_ppe *ppe, 
	int i, sram_num_entries = PPE_SRAM_NUM_ENTRIES;

	struct airoha_foe_entry *hwe = ppe->foe;



	if (airoha_ppe2_is_enabled(ppe->eth))

	if (airoha_ppe_is_enabled(ppe->eth, 1))

		sram_num_entries = sram_num_entries / 2;



	for (i = 0; i < sram_num_entries; i++)