Commit efaa1177 authored Apr 01, 2025 by Ville Syrjälä

drm/i915: Apply the combo PLL frac w/a on DG1



DG1 apparently needs the combo PLL fractional divider w/a
with 38.4 MHz refclk as well. This isn't listed in bspec, but
looking at the hsd it looks like it was possibly just missed
due to no one having a DG1 around at the time.

This gives us slightly more accurate clocks on DG1.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250401163752.6412-2-ville.syrjala@linux.intel.com


Reviewed-by: Imre Deak <imre.deak@intel.com>

parent d35b913f

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

+1 −0

Original line number	Diff line number	Diff line
		@@ -2604,6 +2604,7 @@ ehl_combo_pll_div_frac_wa_needed(struct intel_display *display)
		{
		return ((display->platform.elkhartlake &&
		IS_DISPLAY_STEP(display, STEP_B0, STEP_FOREVER)) \|\|
		display->platform.dg1 \|\|
		display->platform.tigerlake \|\|
		display->platform.alderlake_s \|\|
		display->platform.alderlake_p) &&