Commit efb0c9c0 authored by Kan Liang's avatar Kan Liang Committed by Peter Zijlstra
Browse files

perf/x86/intel/uncore: Factor out common MMIO init and ops functions 



Some uncore PMON registers are located in the MMIO space. For the client
machine, the MMIO space is usually located at D0:F0 but in a different
BAR. For example, some uncore PMON registers are located in the SAF BAR,
not the MCHBAR in the Lunar Lake.

The current __uncore_imc_init_box() hard code the BAR information.
Factor out the uncore_get_box_mmio_addr() which uses the BAR information
as a parameter.
The only change is the error output message. The hardcode name 'MCHBAR'
is replaced by the offset of a BAR.

Add a new macro, MMIO_UNCORE_COMMON_OPS(), since the MMIO ops functions
are usually the same among different generations.

Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20240731141353.759643-2-kan.liang@linux.intel.com
parent e0f49f15

arch/x86/events/intel/uncore_snb.c

+30 −17
Original line number Diff line number Diff line
@@ -1481,33 +1481,35 @@ static struct pci_dev *tgl_uncore_get_mc_dev(void) 
#define TGL_UNCORE_MMIO_IMC_MEM_OFFSET		0x10000

#define TGL_UNCORE_PCI_IMC_MAP_SIZE		0xe000



static void __uncore_imc_init_box(struct intel_uncore_box *box,

				  unsigned int base_offset)

static void

uncore_get_box_mmio_addr(struct intel_uncore_box *box,

			 unsigned int base_offset,

			 int bar_offset, int step)

{

	struct pci_dev *pdev = tgl_uncore_get_mc_dev();

	struct intel_uncore_pmu *pmu = box->pmu;

	struct intel_uncore_type *type = pmu->type;

	resource_size_t addr;

	u32 mch_bar;

	u32 bar;



	if (!pdev) {

		pr_warn("perf uncore: Cannot find matched IMC device.\n");

		return;

	}



	pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET, &mch_bar);

	/* MCHBAR is disabled */

	if (!(mch_bar & BIT(0))) {

		pr_warn("perf uncore: MCHBAR is disabled. Failed to map IMC free-running counters.\n");

	pci_read_config_dword(pdev, bar_offset, &bar);

	if (!(bar & BIT(0))) {

		pr_warn("perf uncore: BAR 0x%x is disabled. Failed to map %s counters.\n",

			bar_offset, type->name);

		pci_dev_put(pdev);

		return;

	}

	mch_bar &= ~BIT(0);

	addr = (resource_size_t)(mch_bar + TGL_UNCORE_MMIO_IMC_MEM_OFFSET * pmu->pmu_idx);

	bar &= ~BIT(0);

	addr = (resource_size_t)(bar + step * pmu->pmu_idx);



#ifdef CONFIG_PHYS_ADDR_T_64BIT

	pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET + 4, &mch_bar);

	addr |= ((resource_size_t)mch_bar << 32);

	pci_read_config_dword(pdev, bar_offset + 4, &bar);

	addr |= ((resource_size_t)bar << 32);

#endif



	addr += base_offset;
@@ -1518,6 +1520,14 @@ static void __uncore_imc_init_box(struct intel_uncore_box *box, 
	pci_dev_put(pdev);

}



static void __uncore_imc_init_box(struct intel_uncore_box *box,

				  unsigned int base_offset)

{

	uncore_get_box_mmio_addr(box, base_offset,

				 SNB_UNCORE_PCI_IMC_BAR_OFFSET,

				 TGL_UNCORE_MMIO_IMC_MEM_OFFSET);

}



static void tgl_uncore_imc_freerunning_init_box(struct intel_uncore_box *box)

{

	__uncore_imc_init_box(box, 0);
@@ -1612,14 +1622,17 @@ static void adl_uncore_mmio_enable_box(struct intel_uncore_box *box) 
	writel(0, box->io_addr + uncore_mmio_box_ctl(box));

}



#define MMIO_UNCORE_COMMON_OPS()				\

	.exit_box	= uncore_mmio_exit_box,		\

	.disable_box	= adl_uncore_mmio_disable_box,	\

	.enable_box	= adl_uncore_mmio_enable_box,	\

	.disable_event	= intel_generic_uncore_mmio_disable_event,	\

	.enable_event	= intel_generic_uncore_mmio_enable_event,	\

	.read_counter	= uncore_mmio_read_counter,



static struct intel_uncore_ops adl_uncore_mmio_ops = {

	.init_box	= adl_uncore_imc_init_box,

	.exit_box	= uncore_mmio_exit_box,

	.disable_box	= adl_uncore_mmio_disable_box,

	.enable_box	= adl_uncore_mmio_enable_box,

	.disable_event	= intel_generic_uncore_mmio_disable_event,

	.enable_event	= intel_generic_uncore_mmio_enable_event,

	.read_counter	= uncore_mmio_read_counter,

	MMIO_UNCORE_COMMON_OPS()

};



#define ADL_UNC_CTL_CHMASK_MASK			0x00000f00