Commit efbdf2e9 authored by Pratyush Yadav's avatar Pratyush Yadav Committed by Nishanth Menon
Browse files

arm64: dts: ti: k3-j7200-som-p0: Add nodes for OSPI0 



TI J7200 has the Cadence OSPI controller for interfacing with OSPI
flashes. Add its node to allow using SPI flashes.

Signed-off-by: default avatarPratyush Yadav <p.yadav@ti.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Reviewed-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20210305153926.3479-4-p.yadav@ti.com
parent 7c172b30

arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi

+17 −0
Original line number Diff line number Diff line
@@ -269,6 +269,23 @@ hbmc: hyperbus@47034000 { 
			#size-cells = <1>;

			mux-controls = <&hbmc_mux 0>;

		};



		ospi0: spi@47040000 {

			compatible = "ti,am654-ospi";

			reg = <0x0 0x47040000 0x0 0x100>,

			      <0x5 0x00000000 0x1 0x0000000>;

			interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;

			cdns,fifo-depth = <256>;

			cdns,fifo-width = <4>;

			cdns,trigger-address = <0x0>;

			clocks = <&k3_clks 103 0>;

			assigned-clocks = <&k3_clks 103 0>;

			assigned-clock-parents = <&k3_clks 103 2>;

			assigned-clock-rates = <166666666>;

			power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;

			#address-cells = <1>;

			#size-cells = <0>;

		};

	};



	tscadc0: tscadc@40200000 {

arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi

+36 −0
Original line number Diff line number Diff line
@@ -100,6 +100,22 @@ J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (A8) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ 
			J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (A7) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */

		>;

	};



	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {

		pinctrl-single,pins = <

			J721E_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* MCU_OSPI0_CLK */

			J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */

			J721E_WKUP_IOPAD(0x000c, PIN_INPUT, 0)  /* MCU_OSPI0_D0 */

			J721E_WKUP_IOPAD(0x0010, PIN_INPUT, 0)  /* MCU_OSPI0_D1 */

			J721E_WKUP_IOPAD(0x0014, PIN_INPUT, 0)  /* MCU_OSPI0_D2 */

			J721E_WKUP_IOPAD(0x0018, PIN_INPUT, 0)  /* MCU_OSPI0_D3 */

			J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0)  /* MCU_OSPI0_D4 */

			J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0)  /* MCU_OSPI0_D5 */

			J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0)  /* MCU_OSPI0_D6 */

			J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0)  /* MCU_OSPI0_D7 */

			J721E_WKUP_IOPAD(0x0008, PIN_INPUT, 0)  /* MCU_OSPI0_DQS */

		>;

	};

};



&main_pmx0 {
@@ -235,3 +251,23 @@ exp_som: gpio@21 { 
				  "GPIO_LIN_EN", "CAN_STB";

	};

};



&ospi0 {

	pinctrl-names = "default";

	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;



	flash@0{

		compatible = "jedec,spi-nor";

		reg = <0x0>;

		spi-tx-bus-width = <8>;

		spi-rx-bus-width = <8>;

		spi-max-frequency = <25000000>;

		cdns,tshsl-ns = <60>;

		cdns,tsd2d-ns = <60>;

		cdns,tchsh-ns = <60>;

		cdns,tslch-ns = <60>;

		cdns,read-delay = <4>;

		#address-cells = <1>;

		#size-cells = <1>;

	};

};