Commit efdb4d23 authored by Tim Harvey's avatar Tim Harvey Committed by Shawn Guo
Browse files

arm64: dts: imx8m{m,n}-venice-gw7902: add SDR50/SDR104 SDIO support for wifi 



The GW7902 has a Murata LBEE5H 802.11abgnac / BT5 module based on the
Cypress CYW43455 which supports SDR50/SDR104.

Add dt pinctrl for the 100mhz and 200mhz states to support SDR50/SDR104.

While at it add the dt node for the CYW43455 wifi.

Signed-off-by: default avatarTim Harvey <tharvey@gateworks.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 18bbf7ac

arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts

+32 −1
Original line number Diff line number Diff line
@@ -714,12 +714,21 @@ &usbotg2 { 


/* SDIO WiFi */

&usdhc2 {

	pinctrl-names = "default";

	pinctrl-names = "default", "state_100mhz", "state_200mhz";

	pinctrl-0 = <&pinctrl_usdhc2>;

	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;

	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;

	bus-width = <4>;

	non-removable;

	vmmc-supply = <&reg_wifi>;

	#address-cells = <1>;

	#size-cells = <0>;

	status = "okay";



	wifi@0 {

		compatible = "brcm,bcm43455-fmac";

		reg = <0>;

	};

};



/* eMMC */
@@ -992,6 +1001,28 @@ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 
		>;

	};



	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {

		fsl,pins = <

			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194

			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4

			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4

			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4

			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4

			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4

		>;

	};



	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {

		fsl,pins = <

			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196

			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6

			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6

			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6

			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6

			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6

		>;

	};



	pinctrl_usdhc3: usdhc3grp {

		fsl,pins = <

			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190

arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts

+32 −1
Original line number Diff line number Diff line
@@ -667,12 +667,21 @@ &usbotg1 { 


/* SDIO WiFi */

&usdhc2 {

	pinctrl-names = "default";

	pinctrl-names = "default", "state_100mhz", "state_200mhz";

	pinctrl-0 = <&pinctrl_usdhc2>;

	pinctrl-1 = <&pinctrl_usdhc2_100mhz>;

	pinctrl-2 = <&pinctrl_usdhc2_200mhz>;

	bus-width = <4>;

	non-removable;

	vmmc-supply = <&reg_wifi>;

	#address-cells = <1>;

	#size-cells = <0>;

	status = "okay";



	wifi@0 {

		compatible = "brcm,bcm43455-fmac";

		reg = <0>;

	};

};



/* eMMC */
@@ -923,6 +932,28 @@ MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 
		>;

	};



	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {

		fsl,pins = <

			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194

			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4

			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4

			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4

			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4

			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4

		>;

	};



	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {

		fsl,pins = <

			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196

			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6

			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6

			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6

			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6

			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6

		>;

	};



	pinctrl_usdhc3: usdhc3grp {

		fsl,pins = <

			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190