Commit efe19d34 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'ata-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux 

Pull ata updates from Damien Le Moal:

 - Simplify ata_print_version_once() using dev_dbg_once() (Heiner)

 - Some cleanups of libata-sata code to simplify the sense data fetching
   code and use BIT() macro for tag bit handling (Niklas)

 - Fix variable name spelling in the sata_sx4 driver (Colin)

 - Improve sense data information field handling for passthrough
   commands (Igor)

 - Add Rockchip RK3576 SoC compatible to the Designware AHCI DT bindings
   (Nicolas)

 - Add a message to indicate if a port is marked as external or not, to
   help with debugging potential issues with LPM (Niklas)

 - Convert DT bindings for "ti,dm816-ahci", "apm,xgene-ahci",
   "cavium,ebt3000-compact-flash", "marvell,orion-sata", and
   "arasan,cf-spear1340" to DT schema (Rob)

 - Cleanup and improve the code and related comments for HIPM and DIPM
   (host initiated and device initiated power managent) handling.

   In particular, keep DIPM disabled while modifying the allowed LPM
   states to avoid races with the device initiating power state changes
   (Niklas)

* tag 'ata-6.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/libata/linux:
  ata: libata-eh: Keep DIPM disabled while modifying the allowed LPM states
  ata: libata-eh: Rename no_dipm variable to be more clear
  ata: libata-eh: Rename hipm and dipm variables
  ata: libata-eh: Add ata_eh_set_lpm() WARN_ON_ONCE
  ata: libata-eh: Update DIPM comments to reflect reality
  dt-bindings: ata: Convert arasan,cf-spear1340 to DT schema
  dt-bindings: ata: Convert marvell,orion-sata to DT schema
  dt-bindings: ata: Convert cavium,ebt3000-compact-flash to DT schema
  dt-bindings: ata: Convert apm,xgene-ahci to DT schema
  dt-bindings: ata: Convert st,ahci to DT schema
  dt-bindings: ata: Convert ti,dm816-ahci to DT schema
  ata: libata: Print if port is external on boot
  dt-bindings: ata: rockchip-dwc-ahci: add RK3576 compatible
  ata: libata-scsi: Do not set the INFORMATION field twice for ATA PT
  ata: sata_sx4: Fix spelling mistake "parttern" -> "pattern"
  ata: libata-sata: Use BIT() macro to convert tag to bit field
  ata: libata-sata: Simplify sense_valid fetching
  ata: libata-core: Simplify ata_print_version_once
parents 76c21d22 a374cfbf

Documentation/devicetree/bindings/ata/ahci-dm816.txt

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Device tree binding for the TI DM816 AHCI SATA Controller

---------------------------------------------------------



Required properties:

  - compatible: must be "ti,dm816-ahci"

  - reg: physical base address and size of the register region used by

         the controller (as defined by the AHCI 1.1 standard)

  - interrupts: interrupt specifier (refer to the interrupt binding)

  - clocks: list of phandle and clock specifier pairs (or only

            phandles for clock providers with '0' defined for

            #clock-cells); two clocks must be specified: the functional

            clock and an external reference clock



Example:



	sata: sata@4a140000 {

		compatible = "ti,dm816-ahci";

		reg = <0x4a140000 0x10000>;

		interrupts = <16>;

		clocks = <&sysclk5_ck>, <&sata_refclk>;

	};

Documentation/devicetree/bindings/ata/ahci-st.txt

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STMicroelectronics STi SATA controller



This binding describes a SATA device.



Required properties:

 - compatible	   : Must be "st,ahci"

 - reg		   : Physical base addresses and length of register sets

 - interrupts	   : Interrupt associated with the SATA device

 - interrupt-names :   Associated name must be; "hostc"

 - clocks	   : The phandle for the clock

 - clock-names	   :   Associated name must be; "ahci_clk"

 - phys		   : The phandle for the PHY port

 - phy-names	   :   Associated name must be; "ahci_phy"



Optional properties:

 - resets	   : The power-down, soft-reset and power-reset lines of SATA IP

 - reset-names	   :   Associated names must be; "pwr-dwn", "sw-rst" and "pwr-rst"



Example:



	/* Example for stih407 family silicon */

	sata0: sata@9b20000 {

		compatible	= "st,ahci";

		reg		= <0x9b20000 0x1000>;

		interrupts	= <GIC_SPI 159 IRQ_TYPE_NONE>;

		interrupt-names	= "hostc";

		phys		= <&phy_port0 PHY_TYPE_SATA>;

		phy-names	= "ahci_phy";

		resets		= <&powerdown STIH407_SATA0_POWERDOWN>,

				  <&softreset STIH407_SATA0_SOFTRESET>,

				  <&softreset STIH407_SATA0_PWR_SOFTRESET>;

		reset-names	= "pwr-dwn", "sw-rst", "pwr-rst";

		clocks		= <&clk_s_c0_flexgen CLK_ICN_REG>;

		clock-names	= "ahci_clk";

	};

Documentation/devicetree/bindings/ata/apm,xgene-ahci.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/ata/apm,xgene-ahci.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: APM X-Gene 6.0 Gb/s SATA host controller



maintainers:

  - Rob Herring <robh@kernel.org>



allOf:

  - $ref: ahci-common.yaml#



properties:

  compatible:

    enum:

      - apm,xgene-ahci

      - apm,xgene-ahci-pcie



  reg:

    minItems: 4

    items:

      - description: AHCI memory resource

      - description: Host controller core

      - description: Host controller diagnostic

      - description: Host controller AXI

      - description: Host controller MUX



  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1



required:

  - compatible

  - clocks

  - phys

  - phy-names



unevaluatedProperties: false



examples:

  - |

    sata@1a400000 {

        compatible = "apm,xgene-ahci";

        reg = <0x1a400000 0x1000>,

              <0x1f220000 0x1000>,

              <0x1f22d000 0x1000>,

              <0x1f22e000 0x1000>,

              <0x1f227000 0x1000>;

        clocks = <&sataclk 0>;

        dma-coherent;

        interrupts = <0x0 0x87 0x4>;

        phys = <&phy2 0>;

        phy-names = "sata-phy";

    };

Documentation/devicetree/bindings/ata/apm-xgene.txt

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* APM X-Gene 6.0 Gb/s SATA host controller nodes



SATA host controller nodes are defined to describe on-chip Serial ATA

controllers. Each SATA controller (pair of ports) have its own node.



Required properties:

- compatible		: Shall contain:

  * "apm,xgene-ahci"

- reg			: First memory resource shall be the AHCI memory

			  resource.

			  Second memory resource shall be the host controller

			  core memory resource.

			  Third memory resource shall be the host controller

			  diagnostic memory resource.

			  4th memory resource shall be the host controller

			  AXI memory resource.

			  5th optional memory resource shall be the host

			  controller MUX memory resource if required.

- interrupts		: Interrupt-specifier for SATA host controller IRQ.

- clocks		: Reference to the clock entry.

- phys			: A list of phandles + phy-specifiers, one for each

			  entry in phy-names.

- phy-names		: Should contain:

  * "sata-phy" for the SATA 6.0Gbps PHY



Optional properties:

- dma-coherent		: Present if dma operations are coherent

- status		: Shall be "ok" if enabled or "disabled" if disabled.

			  Default is "ok".



Example:

		sataclk: sataclk {

			compatible = "fixed-clock";

			#clock-cells = <1>;

			clock-frequency = <100000000>;

			clock-output-names = "sataclk";

		};



		phy2: phy@1f22a000 {

			compatible = "apm,xgene-phy";

			reg = <0x0 0x1f22a000 0x0 0x100>;

			#phy-cells = <1>;

		};



		phy3: phy@1f23a000 {

			compatible = "apm,xgene-phy";

			reg = <0x0 0x1f23a000 0x0 0x100>;

			#phy-cells = <1>;

		};



		sata2: sata@1a400000 {

			compatible = "apm,xgene-ahci";

			reg = <0x0 0x1a400000 0x0 0x1000>,

			      <0x0 0x1f220000 0x0 0x1000>,

			      <0x0 0x1f22d000 0x0 0x1000>,

			      <0x0 0x1f22e000 0x0 0x1000>,

			      <0x0 0x1f227000 0x0 0x1000>;

			interrupts = <0x0 0x87 0x4>;

			dma-coherent;

			clocks = <&sataclk 0>;

			phys = <&phy2 0>;

			phy-names = "sata-phy";

		};



		sata3: sata@1a800000 {

			compatible = "apm,xgene-ahci-pcie";

			reg = <0x0 0x1a800000 0x0 0x1000>,

			      <0x0 0x1f230000 0x0 0x1000>,

			      <0x0 0x1f23d000 0x0 0x1000>,

			      <0x0 0x1f23e000 0x0 0x1000>,

			      <0x0 0x1f237000 0x0 0x1000>;

			interrupts = <0x0 0x88 0x4>;

			dma-coherent;

			clocks = <&sataclk 0>;

			phys = <&phy3 0>;

			phy-names = "sata-phy";

		};

Documentation/devicetree/bindings/ata/arasan,cf-spear1340.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/ata/arasan,cf-spear1340.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Arasan PATA Compact Flash Controller



maintainers:

  - Viresh Kumar <viresh.kumar@linaro.org>



properties:

  compatible:

    const: arasan,cf-spear1340



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  clocks:

    maxItems: 1



  arasan,broken-udma:

    description: UDMA mode is unusable

    type: boolean



  arasan,broken-mwdma:

    description: MWDMA mode is unusable

    type: boolean



  arasan,broken-pio:

    description: PIO mode is unusable

    type: boolean



  dmas:

    maxItems: 1



  dma-names:

    items:

      - const: data



required:

  - compatible

  - reg

  - interrupts



additionalProperties: false



allOf:

  - if:

      not:

        required:

          - arasan,broken-udma

          - arasan,broken-mwdma

    then:

      required:

        - dmas

        - dma-names



examples:

  - |

    cf@fc000000 {

        compatible = "arasan,cf-spear1340";

        reg = <0xfc000000 0x1000>;

        interrupts = <12>;

        dmas = <&dma 23>;

        dma-names = "data";

    };