Commit f046ca4a authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.1-2022-10-19' of... 

Merge tag 'amd-drm-fixes-6.1-2022-10-19' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.1-2022-10-19:

amdgpu:
- Mode2 reset fixes for Sienna Cichlid
- Revert broken fan speed sensor fix
- SMU 13.x fixes
- GC 11.x fixes
- RAS fixes
- SR-IOV fixes
- Fix BO move breakage on SI
- Misc compiler fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221019191357.6208-1-alexander.deucher@amd.com
parents 8865dd75 8273b404

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+0 −4
Original line number Diff line number Diff line
@@ -274,9 +274,6 @@ extern int amdgpu_vcnfw_log; 
#define AMDGPU_RESET_VCE			(1 << 13)

#define AMDGPU_RESET_VCE1			(1 << 14)



#define AMDGPU_RESET_LEVEL_SOFT_RECOVERY (1 << 0)

#define AMDGPU_RESET_LEVEL_MODE2 (1 << 1)



/* max cursor sizes (in pixels) */

#define CIK_CURSOR_WIDTH 128

#define CIK_CURSOR_HEIGHT 128
@@ -1065,7 +1062,6 @@ struct amdgpu_device { 


	struct work_struct		reset_work;



	uint32_t						amdgpu_reset_level_mask;

	bool                            job_hang;

};

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+0 −1
Original line number Diff line number Diff line
@@ -134,7 +134,6 @@ static void amdgpu_amdkfd_reset_work(struct work_struct *work) 
	reset_context.method = AMD_RESET_METHOD_NONE;

	reset_context.reset_req_dev = adev;

	clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);

	clear_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);



	amdgpu_device_gpu_recover(adev, NULL, &reset_context);

}

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.c

+1 −1
Original line number Diff line number Diff line
@@ -111,7 +111,7 @@ static int init_interrupts_v11(struct amdgpu_device *adev, uint32_t pipe_id) 


	lock_srbm(adev, mec, pipe, 0, 0);



	WREG32(SOC15_REG_OFFSET(GC, 0, regCPC_INT_CNTL),

	WREG32_SOC15(GC, 0, regCPC_INT_CNTL,

		CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |

		CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

+0 −2
Original line number Diff line number Diff line
@@ -1954,8 +1954,6 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) 
		return PTR_ERR(ent);

	}



	debugfs_create_u32("amdgpu_reset_level", 0600, root, &adev->amdgpu_reset_level_mask);



	/* Register debugfs entries for amdgpu_ttm */

	amdgpu_ttm_debugfs_init(adev);

	amdgpu_debugfs_pm_init(adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+9 −6
Original line number Diff line number Diff line
@@ -2928,6 +2928,14 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) 
	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);

	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);



	/*

	 * Per PMFW team's suggestion, driver needs to handle gfxoff

	 * and df cstate features disablement for gpu reset(e.g. Mode1Reset)

	 * scenario. Add the missing df cstate disablement here.

	 */

	if (amdgpu_dpm_set_df_cstate(adev, DF_CSTATE_DISALLOW))

		dev_warn(adev->dev, "Failed to disallow df cstate");



	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {

		if (!adev->ip_blocks[i].status.valid)

			continue;
@@ -5210,7 +5218,6 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 


	reset_context->job = job;

	reset_context->hive = hive;



	/*

	 * Build list of devices to reset.

	 * In case we are in XGMI hive mode, resort the device list
@@ -5337,11 +5344,8 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 
			amdgpu_ras_resume(adev);

	} else {

		r = amdgpu_do_asic_reset(device_list_handle, reset_context);

		if (r && r == -EAGAIN) {

			set_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context->flags);

			adev->asic_reset_res = 0;

		if (r && r == -EAGAIN)

			goto retry;

		}



		if (!r && gpu_reset_for_dev_remove)

			goto recover_end;
@@ -5777,7 +5781,6 @@ pci_ers_result_t amdgpu_pci_slot_reset(struct pci_dev *pdev) 
	reset_context.reset_req_dev = adev;

	set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);

	set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);

	set_bit(AMDGPU_SKIP_MODE2_RESET, &reset_context.flags);



	adev->no_hw_access = true;

	r = amdgpu_device_pre_asic_reset(adev, &reset_context);