Commit f0706c04 authored by Daniel Machon's avatar Daniel Machon Committed by Jakub Kicinski
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dt-bindings: net: sparx5: document RGMII delays 



The lan969x switch device supports two RGMII port interfaces that can be
configured for MAC level rx and tx delays. Document two new properties
{rx,tx}-internal-delay-ps in the bindings, used to select these delays.

Tested-by: default avatarRobert Marko <robert.marko@sartura.hr>
Reviewed-by: default avatarRob Herring (Arm) <robh@kernel.org>
Signed-off-by: default avatarDaniel Machon <daniel.machon@microchip.com>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-9-fa8ba5dff732@microchip.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 010fe5df

Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml

+18 −0
Original line number Diff line number Diff line
@@ -129,6 +129,24 @@ properties: 
            minimum: 0

            maximum: 383



          rx-internal-delay-ps:

            description:

              RGMII Receive Clock Delay defined in pico seconds, used to select

              the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and

              3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable

              any delay. The Default is no delay.

            enum: [0, 1000, 1700, 2000, 2500, 3000, 3300]

            default: 0



          tx-internal-delay-ps:

            description:

              RGMII Transmit Clock Delay defined in pico seconds, used to select

              the DLL phase shift between 1000 ps (45 degree shift at 1Gbps) and

              3300 ps (147 degree shift at 1Gbps). A value of 0 ps will disable

              any delay. The Default is no delay.

            enum: [0, 1000, 1700, 2000, 2500, 3000, 3300]

            default: 0



        required:

          - reg

          - phys