Unverified Commit f08e7edb authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-microchip-6.20' of... 

Merge tag 'clk-microchip-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip

Pull Microchip clk driver updates from Claudiu Beznea:

 - clean up microchip/clk-core.c to:
 -- fix a sparse warning related to multiple initializations of
    pic32_sclk_ops.determine_rate()
 -- correct the return values of roclk_get_parent() and sclk_get_parent()
 -- drop an unused include header
 - adjust the PolarFire driver Kconfig section as the driver is now used by
   non-PolarFire devices
 - update the documentation for the Microchip PIC64GX SoC clock controller

* tag 'clk-microchip-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  dt-bindings: clock: mpfs-clkcfg: Add pic64gx compatibility
  dt-bindings: clock: mpfs-ccc: Add pic64gx compatibility
  clk: microchip: drop POLARFIRE from ARCH_MICROCHIP_POLARFIRE
  clk: microchip: core: remove unused include asm/traps.h
  clk: microchip: core: correct return value on *_get_parent()
  clk: microchip: core: remove duplicate determine_rate on pic32_sclk_ops
parents 8f0b4cce ec8c1f35

Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml

+5 −1
Original line number Diff line number Diff line
@@ -17,7 +17,11 @@ description: | 


properties:

  compatible:

    const: microchip,mpfs-ccc

    oneOf:

      - items:

          - const: microchip,pic64gx-ccc

          - const: microchip,mpfs-ccc

      - const: microchip,mpfs-ccc



  reg:

    items:

Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml

+15 −1
Original line number Diff line number Diff line
@@ -19,7 +19,11 @@ description: | 


properties:

  compatible:

    const: microchip,mpfs-clkcfg

    oneOf:

      - items:

          - const: microchip,pic64gx-clkcfg

          - const: microchip,mpfs-clkcfg

      - const: microchip,mpfs-clkcfg



  reg:

    oneOf:
@@ -69,6 +73,16 @@ required: 
  - clocks

  - '#clock-cells'



if:

  properties:

    compatible:

      contains:

        const: microchip,pic64gx-clkcfg

then:

  properties:

    reg:

      maxItems: 1



additionalProperties: false



examples:

drivers/clk/microchip/Kconfig

+2 −2
Original line number Diff line number Diff line
@@ -5,8 +5,8 @@ config COMMON_CLK_PIC32 


config MCHP_CLK_MPFS

	bool "Clk driver for PolarFire SoC"

	depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST

	default ARCH_MICROCHIP_POLARFIRE

	depends on ARCH_MICROCHIP || COMPILE_TEST

	default y

	depends on MFD_SYSCON

	select AUXILIARY_BUS

	select REGMAP_MMIO

drivers/clk/microchip/clk-core.c

+12 −24
Original line number Diff line number Diff line
@@ -10,7 +10,6 @@ 
#include <linux/io.h>

#include <linux/iopoll.h>

#include <asm/mach-pic32/pic32.h>

#include <asm/traps.h>



#include "clk-core.h"
@@ -283,14 +282,13 @@ static u8 roclk_get_parent(struct clk_hw *hw) 


	v = (readl(refo->ctrl_reg) >> REFO_SEL_SHIFT) & REFO_SEL_MASK;



	if (!refo->parent_map)

		return v;



	if (refo->parent_map) {

		for (i = 0; i < clk_hw_get_num_parents(hw); i++)

			if (refo->parent_map[i] == v)

				return i;

	}



	return -EINVAL;

	return v;

}



static unsigned long roclk_calc_rate(unsigned long parent_rate,
@@ -780,15 +778,6 @@ static unsigned long sclk_get_rate(struct clk_hw *hw, unsigned long parent_rate) 
	return parent_rate / div;

}



static int sclk_determine_rate(struct clk_hw *hw,

			       struct clk_rate_request *req)

{

	req->rate = calc_best_divided_rate(req->rate, req->best_parent_rate,

					   SLEW_SYSDIV, 1);



	return 0;

}



static int sclk_set_rate(struct clk_hw *hw,

			 unsigned long rate, unsigned long parent_rate)

{
@@ -826,13 +815,13 @@ static u8 sclk_get_parent(struct clk_hw *hw) 


	v = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK;



	if (!sclk->parent_map)

		return v;



	if (sclk->parent_map) {

		for (i = 0; i < clk_hw_get_num_parents(hw); i++)

			if (sclk->parent_map[i] == v)

				return i;

	return -EINVAL;

	}



	return v;

}



static int sclk_set_parent(struct clk_hw *hw, u8 index)
@@ -912,7 +901,6 @@ static int sclk_init(struct clk_hw *hw) 
const struct clk_ops pic32_sclk_ops = {

	.get_parent	= sclk_get_parent,

	.set_parent	= sclk_set_parent,

	.determine_rate = sclk_determine_rate,

	.set_rate	= sclk_set_rate,

	.recalc_rate	= sclk_get_rate,

	.init		= sclk_init,