Commit f0b19b84 authored by Sathishkumar S's avatar Sathishkumar S Committed by Alex Deucher
Browse files

drm/amdgpu: add amdgpu_jpeg_sched_mask debugfs 



JPEG_4_0_3 has up to 32 jpeg cores and a single mjpeg video decode
will use all available cores on the hardware. This debugfs entry
helps to disable or enable job submission to a cluster of cores or
one specific core in the ip for debugging. The entry is populated
only if there is at least two or more cores in the jpeg ip.

Signed-off-by: default avatarSathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: default avatarLeo Liu <leo.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8b1f7287

drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

+2 −0
Original line number Diff line number Diff line
@@ -2095,6 +2095,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) 
	if (amdgpu_umsch_mm & amdgpu_umsch_mm_fwlog)

		amdgpu_debugfs_umsch_fwlog_init(adev, &adev->umsch_mm);



	amdgpu_debugfs_jpeg_sched_mask_init(adev);



	amdgpu_ras_debugfs_create_all(adev);

	amdgpu_rap_debugfs_init(adev);

	amdgpu_securedisplay_debugfs_init(adev);

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c

+73 −0
Original line number Diff line number Diff line
@@ -342,3 +342,76 @@ int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx, 


	return psp_execute_ip_fw_load(&adev->psp, &ucode);

}



/*

 * debugfs for to enable/disable jpeg job submission to specific core.

 */

#if defined(CONFIG_DEBUG_FS)

static int amdgpu_debugfs_jpeg_sched_mask_set(void *data, u64 val)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)data;

	u32 i, j;

	u64 mask = 0;

	struct amdgpu_ring *ring;



	if (!adev)

		return -ENODEV;



	mask = (1 << (adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings)) - 1;

	if ((val & mask) == 0)

		return -EINVAL;



	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {

		for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {

			ring = &adev->jpeg.inst[i].ring_dec[j];

			if (val & (1 << ((i * adev->jpeg.num_jpeg_rings) + j)))

				ring->sched.ready = true;

			else

				ring->sched.ready = false;

		}

	}

	/* publish sched.ready flag update effective immediately across smp */

	smp_rmb();

	return 0;

}



static int amdgpu_debugfs_jpeg_sched_mask_get(void *data, u64 *val)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)data;

	u32 i, j;

	u64 mask = 0;

	struct amdgpu_ring *ring;



	if (!adev)

		return -ENODEV;

	for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {

		for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {

			ring = &adev->jpeg.inst[i].ring_dec[j];

			if (ring->sched.ready)

				mask |= 1 << ((i * adev->jpeg.num_jpeg_rings) + j);

		}

	}

	*val = mask;

	return 0;

}



DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_jpeg_sched_mask_fops,

			 amdgpu_debugfs_jpeg_sched_mask_get,

			 amdgpu_debugfs_jpeg_sched_mask_set, "%llx\n");



#endif



void amdgpu_debugfs_jpeg_sched_mask_init(struct amdgpu_device *adev)

{

#if defined(CONFIG_DEBUG_FS)

	struct drm_minor *minor = adev_to_drm(adev)->primary;

	struct dentry *root = minor->debugfs_root;

	char name[32];



	if (!(adev->jpeg.num_jpeg_inst > 1) && !(adev->jpeg.num_jpeg_rings > 1))

		return;

	sprintf(name, "amdgpu_jpeg_sched_mask");

	debugfs_create_file(name, 0600, root, adev,

			    &amdgpu_debugfs_jpeg_sched_mask_fops);

#endif

}

drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h

+1 −0
Original line number Diff line number Diff line
@@ -149,5 +149,6 @@ int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev, 
int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev);

int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx,

			       enum AMDGPU_UCODE_ID ucode_id);

void amdgpu_debugfs_jpeg_sched_mask_init(struct amdgpu_device *adev);



#endif /*__AMDGPU_JPEG_H__*/