Commit f0bbfc39 authored by Xin Zeng's avatar Xin Zeng Committed by Herbert Xu
Browse files

crypto: qat - implement interface for live migration 



Add logic to implement the interface for live migration defined in
qat/qat_mig_dev.h. This is specific for QAT GEN4 Virtual Functions
(VFs).

This introduces a migration data manager which is used to handle the
device state during migration. The manager ensures that the device state
is stored in a format that can be restored in the destination node.

The VF state is organized into a hierarchical structure that includes a
preamble, a general state section, a MISC bar section and an ETR bar
section. The latter contains the state of the 4 ring pairs contained on
a VF. Here is a graphical representation of the state:

    preamble | general state section | leaf state
             | MISC bar state section| leaf state
             | ETR bar state section | bank0 state section | leaf state
                                     | bank1 state section | leaf state
                                     | bank2 state section | leaf state
                                     | bank3 state section | leaf state

In addition to the implementation of the qat_migdev_ops interface and
the state manager framework, add a mutex in pfvf to avoid pf2vf messages
during migration.

Signed-off-by: default avatarXin Zeng <xin.zeng@intel.com>
Reviewed-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 0fce55e5

drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c

+2 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include <adf_gen4_ras.h>

#include <adf_gen4_timer.h>

#include <adf_gen4_tl.h>

#include <adf_gen4_vf_mig.h>

#include "adf_420xx_hw_data.h"

#include "icp_qat_hw.h"
@@ -488,6 +489,7 @@ void adf_init_hw_data_420xx(struct adf_hw_device_data *hw_data, u32 dev_id) 
	adf_gen4_init_dc_ops(&hw_data->dc_ops);

	adf_gen4_init_ras_ops(&hw_data->ras_ops);

	adf_gen4_init_tl_data(&hw_data->tl_data);

	adf_gen4_init_vf_mig_ops(&hw_data->vfmig_ops);

	adf_init_rl_data(&hw_data->rl_data);

}

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

+2 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include "adf_gen4_ras.h"

#include <adf_gen4_timer.h>

#include <adf_gen4_tl.h>

#include <adf_gen4_vf_mig.h>

#include "adf_4xxx_hw_data.h"

#include "icp_qat_hw.h"
@@ -472,6 +473,7 @@ void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 dev_id) 
	adf_gen4_init_dc_ops(&hw_data->dc_ops);

	adf_gen4_init_ras_ops(&hw_data->ras_ops);

	adf_gen4_init_tl_data(&hw_data->tl_data);

	adf_gen4_init_vf_mig_ops(&hw_data->vfmig_ops);

	adf_init_rl_data(&hw_data->rl_data);

}

drivers/crypto/intel/qat/qat_common/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -20,12 +20,14 @@ intel_qat-objs := adf_cfg.o \ 
	adf_gen4_config.o \

	adf_gen4_hw_csr_data.o \

	adf_gen4_hw_data.o \

	adf_gen4_vf_mig.o \

	adf_gen4_pm.o \

	adf_gen2_dc.o \

	adf_gen4_dc.o \

	adf_gen4_ras.o \

	adf_gen4_timer.o \

	adf_clock.o \

	adf_mstate_mgr.o \

	qat_crypto.o \

	qat_compression.o \

	qat_comp_algs.o \

drivers/crypto/intel/qat/qat_common/adf_accel_devices.h

+6 −0
Original line number Diff line number Diff line
@@ -412,11 +412,17 @@ struct adf_fw_loader_data { 
struct adf_accel_vf_info {

	struct adf_accel_dev *accel_dev;

	struct mutex pf2vf_lock; /* protect CSR access for PF2VF messages */

	struct mutex pfvf_mig_lock; /* protects PFVF state for migration */

	struct ratelimit_state vf2pf_ratelimit;

	u32 vf_nr;

	bool init;

	bool restarting;

	u8 vf_compat_ver;

	/*

	 * Private area used for device migration.

	 * Memory allocation and free is managed by migration driver.

	 */

	void *mig_priv;

};



struct adf_dc_data {

drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.h

+10 −0
Original line number Diff line number Diff line
@@ -86,6 +86,7 @@ 
#define ADF_RP_INT_SRC_SEL_F_RISE_MASK	BIT(2)

#define ADF_RP_INT_SRC_SEL_F_FALL_MASK	GENMASK(2, 0)

#define ADF_RP_INT_SRC_SEL_RANGE_WIDTH	4

#define ADF_COALESCED_POLL_TIMEOUT_US	(1 * USEC_PER_SEC)

#define ADF_COALESCED_POLL_DELAY_US	1000

#define ADF_WQM_CSR_RPINTSOU(bank)	(0x200000 + ((bank) << 12))

#define ADF_WQM_CSR_RP_IDX_RX		1
@@ -120,6 +121,15 @@ 
/* PF2VM communication channel */

#define ADF_GEN4_PF2VM_OFFSET(i)	(0x40B010 + (i) * 0x20)

#define ADF_GEN4_VM2PF_OFFSET(i)	(0x40B014 + (i) * 0x20)

#define ADF_GEN4_VINTMSKPF2VM_OFFSET(i)	(0x40B00C + (i) * 0x20)

#define ADF_GEN4_VINTSOUPF2VM_OFFSET(i)	(0x40B008 + (i) * 0x20)

#define ADF_GEN4_VINTMSK_OFFSET(i)	(0x40B004 + (i) * 0x20)

#define ADF_GEN4_VINTSOU_OFFSET(i)	(0x40B000 + (i) * 0x20)



struct adf_gen4_vfmig {

	struct adf_mstate_mgr *mstate_mgr;

	bool bank_stopped[ADF_GEN4_NUM_BANKS_PER_VF];

};



void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev);