Commit f0c6b79b authored by Sunil Khatri's avatar Sunil Khatri Committed by Alex Deucher
Browse files

drm/amdgpu: enable redirection of irq's for IH v7.0 



Enable redirection of irq for pagefaults for specific
clients to avoid overflow without dropping interrupts.

So here we redirect the interrupts to another IH ring
i.e ring1 where only these interrupts are processed.

Signed-off-by: default avatarSunil Khatri <sunil.khatri@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 906219ec

drivers/gpu/drm/amd/amdgpu/ih_v7_0.c

+15 −0
Original line number Diff line number Diff line
@@ -346,6 +346,21 @@ static int ih_v7_0_irq_init(struct amdgpu_device *adev) 
			    DELAY, 3);

	WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);



	/* Redirect the interrupts to IH RB1 for dGPU */

	if (adev->irq.ih1.ring_size) {

		tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);

		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);

		WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp);



		tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);

		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);

		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);

		tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,

				    SOURCE_ID_MATCH_ENABLE, 0x1);



		WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp);

	}



	pci_set_master(adev->pdev);



	/* enable interrupts */