Commit f0fbbff7 authored by Alexandre Courbot's avatar Alexandre Courbot
Browse files

gpu: nova-core: require `Send` on `FalconEngine` and `FalconHal` 



We want to store the GSP and SEC2 falcon instances inside the `Gpu`
structure, but doing so require these types to implement `Send` for
`pci::Driver` to remain implementable on `NovaCore`, which embeds `Gpu`.

All implementors of `FalconEngine` and `FalconHal` satisfy the
requirements of `Send`, and these traits also already required `Sync`,
so this a minor tweak.

Acked-by: default avatarDanilo Krummrich <dakr@kernel.org>
Link: https://lore.kernel.org/r/20250913-nova_firmware-v6-1-9007079548b0@nvidia.com


Signed-off-by: default avatarAlexandre Courbot <acourbot@nvidia.com>
parent 37604019

drivers/gpu/nova-core/falcon.rs

+1 −1
Original line number Diff line number Diff line
@@ -286,7 +286,7 @@ fn from(value: bool) -> Self { 
/// Each engine provides one base for `PFALCON` and `PFALCON2` registers. The `ID` constant is used

/// to identify a given Falcon instance with register I/O methods.

pub(crate) trait FalconEngine:

    Sync + RegisterBase<PFalconBase> + RegisterBase<PFalcon2Base> + Sized

    Send + Sync + RegisterBase<PFalconBase> + RegisterBase<PFalcon2Base> + Sized

{

    /// Singleton of the engine, used to identify it with register I/O methods.

    const ID: Self;

drivers/gpu/nova-core/falcon/hal.rs

+1 −1
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 
/// Implements chipset-specific low-level operations. The trait is generic against [`FalconEngine`]

/// so its `BASE` parameter can be used in order to avoid runtime bound checks when accessing

/// registers.

pub(crate) trait FalconHal<E: FalconEngine>: Sync {

pub(crate) trait FalconHal<E: FalconEngine>: Send + Sync {

    /// Activates the Falcon core if the engine is a risvc/falcon dual engine.

    fn select_core(&self, _falcon: &Falcon<E>, _bar: &Bar0) -> Result {

        Ok(())