Commit f13ee7cc authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull thermal control updates from Rafael Wysocki:
 "These are mostly thermal driver updates, including new thermal drivers
  for Renesas RZ/G3S and Renesas RZ/G3E SoCs, a new power slider
  platform feature support in the Intel int340x thermal driver, a new
  Tegra114- specific SOCTHERM driver and more.

  There is also a Step-wise thermal governor update allowing it to start
  reducing cooling somewhat earlier if the temperature of the given
  thermal zone is falling down and a thermal testing code cleanup.

  Specifics:

   - Add new thermal driver for the Renesas RZ/G3S SoC (Claudiu Beznea)

   - Add new thermal driver for the Renesas RZ/G3E SoC (John Madieu)

   - Add support for new platform power slider feature to the Intel
     int340x driver (Srinivas Pandruvada).

   - Add new Tegra114-specific SOCTHERM driver and document Tegra114
     SOCTHERM Thermal Management System in DT bindings (Svyatoslav
     Ryhel)

   - Add temperature sensor channel to thermal-generic-adc (Svyatoslav
     Ryhel)

   - Add support for per-SoC default trim values to the Renesas
     rcar_gen3 thermal driver, use it for adding R-Car V4H default trim
     values, fix a comment typo in that driver and document Gen4 support
     in its Kconfig entry (Marek Vasut)

   - Fix mapping SoCs to generic Gen4 entry in the Renesas rcar_gen3
     thermal driver (Wolfram Sang)

   - Document the TSU unit in the r9a08g045-tsu and r9a09g047-tsu DT
     bindings (Claudiu Beznea, John Madieu)

   - Make LMH select QCOM_SCM and add missing IRQ includes to the
     qcom/lmh thermal driver (Dmitry Baryshkov)

   - Fix incorrect error message in the qcom/lmh thermal driver (Sumeet
     Pawnikar)

   - Add QCS615 compatible to tsens thermal DT bindings (Gaurav Kohli)

   - Document the Glymur temperature sensor in qcom-tsens thermal DT
     bindings (Manaf Meethalavalappu Pallikunhi)

   - Make k3_j72xx_bandgap thermal driver register the thermal sensor
     with hwmon (Michael Walle)

   - Tighten GRF requirements in the rockchip thermal DT bindings,
     silence a GRF warning in the rockchip thermal driver and unify
     struct rockchip_tsadc_chip format in it (Sebastian Reichel)

   - Update the Step-wise thermal governor to allow it to reduce the
     cooling level earlier if thermal zone temperature is dropping and
     clean it up (Rafael Wysocki)

   - Clean up the thermal testing code (Rafael Wysocki)

   - Assorted cleanups of thermal drivers (Jiapeng Chong, Salah Triki,
     Osama Abdelkader)"

* tag 'thermal-6.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (37 commits)
  thermal/drivers/renesas/rzg3e: Fix add thermal driver for the Renesas RZ/G3E SoC
  dt-bindings: thermal: qcom-tsens: Document the Glymur temperature Sensor
  thermal/drivers/renesas/rzg3e: Add thermal driver for the Renesas RZ/G3E SoC
  dt-bindings: thermal: r9a09g047-tsu: Document the TSU unit
  thermal/drivers/thermal-generic-adc: Add temperature sensor channel
  dt-bindings: thermal: rockchip: Tighten grf requirements
  thermal/drivers/rockchip: Shut up GRF warning
  thermal/drivers/rockchip: Unify struct rockchip_tsadc_chip format
  thermal/drivers/renesas/rzg3s: Add thermal driver for the Renesas RZ/G3S SoC
  dt-bindings: thermal: r9a08g045-tsu: Document the TSU unit
  thermal/drivers/k3_j72xx_bandgap: Register sensors with hwmon
  thermal/drivers/rcar_gen3: Fix mapping SoCs to generic Gen4 entry
  thermal/drivers/tegra: Add Tegra114 specific SOCTHERM driver
  dt-bindings: thermal: add Tegra114 soctherm header
  thermal/drivers/tegra/soctherm-fuse: Prepare calibration for Tegra114 support
  dt-bindings: thermal: Document Tegra114 SOCTHERM Thermal Management System
  thermal/drivers/rcar_gen3: Document Gen4 support in Kconfig entry
  thermal/drivers/rcar_gen3: Fix comment typo
  drivers/thermal/qcom/lmh: Fix incorrect error message
  thermal/drivers/qcom/lmh: Add missing IRQ includes
  ...
parents 679a1639 2085f0f4
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+2 −0
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@@ -18,6 +18,7 @@ description: The SOCTHERM IP block contains thermal sensors, support for
properties:
  compatible:
    enum:
      - nvidia,tegra114-soctherm
      - nvidia,tegra124-soctherm
      - nvidia,tegra132-soctherm
      - nvidia,tegra210-soctherm
@@ -206,6 +207,7 @@ allOf:
        compatible:
          contains:
            enum:
              - nvidia,tegra114-soctherm
              - nvidia,tegra124-soctherm
              - nvidia,tegra210-soctherm
              - nvidia,tegra210b01-soctherm
+2 −0
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@@ -49,11 +49,13 @@ properties:
      - description: v2 of TSENS
        items:
          - enum:
              - qcom,glymur-tsens
              - qcom,milos-tsens
              - qcom,msm8953-tsens
              - qcom,msm8996-tsens
              - qcom,msm8998-tsens
              - qcom,qcm2290-tsens
              - qcom,qcs615-tsens
              - qcom,sa8255p-tsens
              - qcom,sa8775p-tsens
              - qcom,sar2130p-tsens
+93 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/renesas,r9a08g045-tsu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/G3S Thermal Sensor Unit

description:
  The thermal sensor unit (TSU) measures the temperature(Tj) inside
  the LSI.

maintainers:
  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>

$ref: thermal-sensor.yaml#

properties:
  compatible:
    const: renesas,r9a08g045-tsu

  reg:
    maxItems: 1

  clocks:
    items:
      - description: TSU module clock

  power-domains:
    maxItems: 1

  resets:
    items:
      - description: TSU module reset

  io-channels:
    items:
      - description: ADC channel which reports the TSU temperature

  io-channel-names:
    items:
      - const: tsu

  "#thermal-sensor-cells":
    const: 0

required:
  - compatible
  - reg
  - clocks
  - power-domains
  - resets
  - io-channels
  - io-channel-names
  - '#thermal-sensor-cells'

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/r9a08g045-cpg.h>

    tsu: thermal@10059000 {
        compatible = "renesas,r9a08g045-tsu";
        reg = <0x10059000 0x1000>;
        clocks = <&cpg CPG_MOD R9A08G045_TSU_PCLK>;
        resets = <&cpg R9A08G045_TSU_PRESETN>;
        power-domains = <&cpg>;
        #thermal-sensor-cells = <0>;
        io-channels = <&adc 8>;
        io-channel-names = "tsu";
    };

    thermal-zones {
        cpu-thermal {
            polling-delay-passive = <250>;
            polling-delay = <1000>;
            thermal-sensors = <&tsu>;

            trips {
                sensor_crit: sensor-crit {
                    temperature = <125000>;
                    hysteresis = <1000>;
                    type = "critical";
                };
                target: trip-point {
                    temperature = <100000>;
                    hysteresis = <1000>;
                    type = "passive";
                };
            };
        };
    };
+87 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/thermal/renesas,r9a09g047-tsu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas RZ/G3E Temperature Sensor Unit (TSU)

maintainers:
  - John Madieu <john.madieu.xa@bp.renesas.com>

description:
  The Temperature Sensor Unit (TSU) is an integrated thermal sensor that
  monitors the chip temperature on the Renesas RZ/G3E SoC. The TSU provides
  real-time temperature measurements for thermal management.

properties:
  compatible:
    const: renesas,r9a09g047-tsu

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  power-domains:
    maxItems: 1

  interrupts:
    items:
      - description: Conversion complete interrupt signal (pulse)
      - description: Comparison result interrupt signal (level)

  interrupt-names:
    items:
      - const: adi
      - const: adcmpi

  "#thermal-sensor-cells":
    const: 0

  renesas,tsu-trim:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    items:
      - items:
          - description: phandle to system controller
          - description: offset of trim registers
    description:
      Phandle and offset to the system controller containing the TSU
      calibration trim values. The offset points to the first trim register
      (OTPTSU1TRMVAL0), with the second trim register (OTPTSU1TRMVAL1) located
      at offset + 4.

required:
  - compatible
  - reg
  - clocks
  - resets
  - power-domains
  - interrupts
  - interrupt-names
  - "#thermal-sensor-cells"
  - renesas,tsu-trim

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    thermal-sensor@14002000 {
        compatible = "renesas,r9a09g047-tsu";
        reg = <0x14002000 0x1000>;
        clocks = <&cpg CPG_MOD 0x10a>;
        resets = <&cpg 0xf8>;
        power-domains = <&cpg>;
        interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
                     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-names = "adi", "adcmpi";
        #thermal-sensor-cells = <0>;
        renesas,tsu-trim = <&sys 0x330>;
    };
+15 −0
Original line number Diff line number Diff line
@@ -119,6 +119,21 @@ required:
  - resets

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - rockchip,px30-tsadc
              - rockchip,rk3366-tsadc
              - rockchip,rk3399-tsadc
              - rockchip,rk3568-tsadc
    then:
      required:
        - rockchip,grf
    else:
      properties:
        rockchip,grf: false
  - if:
      not:
        properties:
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