Commit f1a024f7 authored by Jan Kiszka's avatar Jan Kiszka Committed by Vignesh Raghavendra
Browse files

arm64: dts: ti: iot2050: Factor out enabling of USB3 support 



Already simplifies the existing code by avoid the switch back in the m2
variant to what k3-am65-main.dtsi provided as base.

Signed-off-by: default avatarJan Kiszka <jan.kiszka@siemens.com>
Link: https://lore.kernel.org/r/51d9be5ddbf74f90bc915ab5473b9ea9a4b0cdf7.1707463401.git.jan.kiszka@siemens.com


Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
parent 1ef134a4

arch/arm64/boot/dts/ti/k3-am65-iot2050-common-pg2.dtsi

+0 −18
Original line number Diff line number Diff line
@@ -38,21 +38,3 @@ &dss { 
	/* Workaround needed to get DP clock of 154Mhz */

	assigned-clocks = <&k3_clks 67 0>;

};
 


&serdes0 {

	assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;

	assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;

};



&dwc3_0 {

	assigned-clock-parents = <&k3_clks 151 4>,  /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */

				 <&k3_clks 151 8>;  /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */

	phys = <&serdes0 PHY_TYPE_USB3 0>;

	phy-names = "usb3-phy";

};



&usb0 {

	maximum-speed = "super-speed";

	snps,dis-u1-entry-quirk;

	snps,dis-u2-entry-quirk;

};

arch/arm64/boot/dts/ti/k3-am65-iot2050-usb3.dtsi

0 → 100644
+27 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) Siemens AG, 2024

 *

 * Authors:

 *   Jan Kiszka <jan.kiszka@siemens.com>

 *

 * Common bits for IOT2050 variants with USB3 support

 */



&serdes0 {

	assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;

	assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>;

};



&dwc3_0 {

	assigned-clock-parents = <&k3_clks 151 4>,  /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */

				 <&k3_clks 151 8>;  /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */

	phys = <&serdes0 PHY_TYPE_USB3 0>;

	phy-names = "usb3-phy";

};



&usb0 {

	maximum-speed = "super-speed";

	snps,dis-u1-entry-quirk;

	snps,dis-u2-entry-quirk;

};

arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-pg2.dts

+1 −0
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 


#include "k3-am6528-iot2050-basic-common.dtsi"

#include "k3-am65-iot2050-common-pg2.dtsi"

#include "k3-am65-iot2050-usb3.dtsi"



/ {

	compatible = "siemens,iot2050-basic-pg2", "ti,am654";

arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-m2.dts

+0 −13
Original line number Diff line number Diff line
@@ -92,16 +92,3 @@ &pcie0_rc { 
&pcie1_rc {

	status = "disabled";

};
 


&dwc3_0 {

	assigned-clock-parents = <&k3_clks 151 4>,  /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */

				 <&k3_clks 151 9>;  /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */

	/delete-property/ phys;

	/delete-property/ phy-names;

};



&usb0 {

	maximum-speed = "high-speed";

	/delete-property/ snps,dis-u1-entry-quirk;

	/delete-property/ snps,dis-u2-entry-quirk;

};

arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-pg2.dts

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#include "k3-am6548-iot2050-advanced-common.dtsi"

#include "k3-am65-iot2050-common-pg2.dtsi"

#include "k3-am65-iot2050-arduino-connector.dtsi"

#include "k3-am65-iot2050-usb3.dtsi"



/ {

	compatible = "siemens,iot2050-advanced-pg2", "ti,am654";