Commit f1a9e82a authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-6.2-2023-02-01' of... 

Merge tag 'amd-drm-fixes-6.2-2023-02-01' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-6.2-2023-02-01:

amdgpu:
- GC11 fixes
- DCN 3.1.4 fixes
- NBIO 4.3 fix
- DCN 3.2 fixes
- Properly handle additional cases where DCN is not supported
- SMU13 fixes

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230202042309.24144-1-alexander.deucher@amd.com
parents 74d6c8ea 6fc547a5

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+2 −2
Original line number Diff line number Diff line
@@ -790,8 +790,8 @@ static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, 
	 * zero here */

	WARN_ON(simd != 0);



	/* type 2 wave data */

	dst[(*no_fields)++] = 2;

	/* type 3 wave data */

	dst[(*no_fields)++] = 3;

	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);

	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);

	dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);

drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c

+7 −1
Original line number Diff line number Diff line
@@ -337,7 +337,13 @@ const struct nbio_hdp_flush_reg nbio_v4_3_hdp_flush_reg = { 


static void nbio_v4_3_init_registers(struct amdgpu_device *adev)

{

	return;

	if (adev->ip_versions[NBIO_HWIP][0] == IP_VERSION(4, 3, 0)) {

		uint32_t data;



		data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2);

		data &= ~RCC_DEV0_EPF2_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F2_MASK;

		WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF2_STRAP2, data);

	}

}



static u32 nbio_v4_3_get_rom_offset(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/soc21.c

+2 −1
Original line number Diff line number Diff line
@@ -640,7 +640,8 @@ static int soc21_common_early_init(void *handle) 
			AMD_CG_SUPPORT_GFX_CGCG |

			AMD_CG_SUPPORT_GFX_CGLS |

			AMD_CG_SUPPORT_REPEATER_FGCG |

			AMD_CG_SUPPORT_GFX_MGCG;

			AMD_CG_SUPPORT_GFX_MGCG |

			AMD_CG_SUPPORT_HDP_SD;

		adev->pg_flags = AMD_PG_SUPPORT_VCN |

			AMD_PG_SUPPORT_VCN_DPG |

			AMD_PG_SUPPORT_JPEG;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+11 −0
Original line number Diff line number Diff line
@@ -4501,6 +4501,17 @@ DEVICE_ATTR_WO(s3_debug); 
static int dm_early_init(void *handle)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;

	struct amdgpu_mode_info *mode_info = &adev->mode_info;

	struct atom_context *ctx = mode_info->atom_context;

	int index = GetIndexIntoMasterTable(DATA, Object_Header);

	u16 data_offset;



	/* if there is no object header, skip DM */

	if (!amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {

		adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK;

		dev_info(adev->dev, "No object header, skipping DM\n");

		return -ENOENT;

	}



	switch (adev->asic_type) {

#if defined(CONFIG_DRM_AMD_DC_SI)

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c

+3 −2
Original line number Diff line number Diff line
@@ -874,8 +874,9 @@ static const struct dc_plane_cap plane_cap = { 
	},



	// 6:1 downscaling ratio: 1000/6 = 166.666

	// 4:1 downscaling ratio for ARGB888 to prevent underflow during P010 playback: 1000/4 = 250

	.max_downscale_factor = {

			.argb8888 = 167,

			.argb8888 = 250,

			.nv12 = 167,

			.fp16 = 167

	},
@@ -1763,7 +1764,7 @@ static bool dcn314_resource_construct( 
	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;

	pool->base.pipe_count = pool->base.res_cap->num_timing_generator;

	pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;

	dc->caps.max_downscale_ratio = 600;

	dc->caps.max_downscale_ratio = 400;

	dc->caps.i2c_speed_in_khz = 100;

	dc->caps.i2c_speed_in_khz_hdcp = 100;

	dc->caps.max_cursor_size = 256;