Commit f1e6f895 authored by Pallavi Mishra's avatar Pallavi Mishra Committed by Matt Roper
Browse files

drm/xe/xe2: Enable Priority Mem Read 



Enable feature to allow memory reads to take a priority memory path.
This will reduce latency on the read path, but may introduce read after
write (RAW) hazards as read and writes will no longer be ordered.

To avoid RAW hazards, SW can use the MI_MEM_FENCE command or any other
MI command that generates non posted memory writes.  This will ensure
data is coherent in memory prior to execution of commands which read
data from memory. RCS,BCS and CCS support this feature.

No pattern identified in KMD that could lead to a hazard.

v2: Modify commit message, enable priority mem read feature for media,
modify version range, modify bspec detail (Matt Roper)

v3: Rebase, fix cramped line-wrapping (jcavitt)

v4: Rebase

v5: Media does not support Priority Mem Read. Modify commit
to reflect the same.

v6: Rebase

Bspec: 60298, 60237, 60187, 60188

Signed-off-by: default avatarPallavi Mishra <pallavi.mishra@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Acked-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Acked-by: default avatarCarl Zhang <carl.zhang@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240731195622.1868401-1-pallavi.mishra@intel.com
parent 6f20fc09

drivers/gpu/drm/xe/regs/xe_engine_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -104,6 +104,7 @@ 
#define CSFE_CHICKEN1(base)			XE_REG((base) + 0xd4, XE_REG_OPTION_MASKED)

#define   GHWSP_CSB_REPORT_DIS			REG_BIT(15)

#define   PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS	REG_BIT(14)

#define   CS_PRIORITY_MEM_READ			REG_BIT(7)



#define FF_SLICE_CS_CHICKEN1(base)		XE_REG((base) + 0xe0, XE_REG_OPTION_MASKED)

#define   FFSC_PERCTX_PREEMPT_CTRL		REG_BIT(14)

drivers/gpu/drm/xe/xe_hw_engine.c

+6 −0
Original line number Diff line number Diff line
@@ -428,6 +428,12 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe) 
					   0xA,

					   XE_RTP_ACTION_FLAG(ENGINE_BASE)))

		},

		/* Enable Priority Mem Read */

		{ XE_RTP_NAME("Priority_Mem_Read"),

		  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED)),

		  XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), CS_PRIORITY_MEM_READ,

				     XE_RTP_ACTION_FLAG(ENGINE_BASE)))

		},

		{}

	};