Commit f20ca899 authored by Ville Syrjälä's avatar Ville Syrjälä
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drm/i915: Stop using group access when progrmming icl combo phy TX



Program each TX lane individually so that we can start to use per-lane
drive settings.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211006204937.30774-8-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
parent 565edeee
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+16 −12
Original line number Diff line number Diff line
@@ -1069,14 +1069,16 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
	intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);

	/* Program PORT_TX_DW2 */
	val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
	for (ln = 0; ln < 4; ln++) {
		val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy));
		val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
			 RCOMP_SCALAR_MASK);
		val |= SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel);
		val |= SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel);
		/* Program Rcomp scalar for every table entry */
		val |= RCOMP_SCALAR(0x98);
	intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
		intel_de_write(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), val);
	}

	/* Program PORT_TX_DW4 */
	/* We cannot write to GRP. It would overwrite individual loadgen. */
@@ -1091,10 +1093,12 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
	}

	/* Program PORT_TX_DW7 */
	val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN(0, phy));
	for (ln = 0; ln < 4; ln++) {
		val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy));
		val &= ~N_SCALAR_MASK;
		val |= N_SCALAR(trans->entries[level].icl.dw7_n_scalar);
	intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
		intel_de_write(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), val);
	}
}

static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,