Commit f21923f3 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
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dt-bindings: clock: renesas,r9a09g047-cpg: Add XSPI and GBETH PTP core clocks 



Add definitions for XSPI core clock and Gigabit Ethernet PTP reference
core clocks in the R9A09G047 CPG DT bindings header file.

The clk_spi is modelled as a fixed divider clock with parent clk_spix2 and
factor two as both parent and child share same gating bit.

Signed-off-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250424081400.135028-2-biju.das.jz@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 5c7fb203

include/dt-bindings/clock/renesas,r9a09g047-cpg.h

+3 −0
Original line number Diff line number Diff line
@@ -17,5 +17,8 @@ 
#define R9A09G047_CM33_CLK0			6

#define R9A09G047_CST_0_SWCLKTCK		7

#define R9A09G047_IOTOP_0_SHCLK			8

#define R9A09G047_SPI_CLK_SPI			9

#define R9A09G047_GBETH_0_CLK_PTP_REF_I		10

#define R9A09G047_GBETH_1_CLK_PTP_REF_I		11



#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */