Commit f31fd0b3 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'pcs-xpcs-cleanups-batch-2' 



Russell King says:

====================
net: pcs: xpcs: cleanups batch 2

This is the second cleanup series for XPCS.

Patch 1 removes the enum indexing the dw_xpcs_compat array. The index is
never used except to place entries in the array and to size the array.

Patch 2 removes the interface arrays - each of which only contain one
interface.

Patch 3 makes xpcs_find_compat() take the xpcs structure rather than the
ID - the previous series removed the reason for xpcs_find_compat needing
to take the ID.

Patch 4 provides a helper to convert xpcs structure to a regular
phylink_pcs structure, which leads to patch 5.

Patch 5 moves the definition of struct dw_xpcs to the private xpcs
header - with patch 4 in place, nothing outside of the xpcs driver
accesses the contents of the dw_xpcs structure.

Patch 6 renames xpcs_get_id() to xpcs_read_id() since it's reading the
ID, rather than doing anything further with it. (Prior versions of this
series renamed it to xpcs_read_phys_id() since that more accurately
described that it was reading the physical ID registers.)

Patch 7 moves the searching of the ID list out of line as this is a
separate functional block.

Patch 8 converts xpcs to use the bitmap macros, which eliminates the
need for _SHIFT definitions.

Patch 9 adds and uses _modify() accessors as there are a large amount
of read-modify-write operations in this driver. This conversion found
a bug in xpcs-wx code that has been reported and already fixed.

Patch 10 converts xpcs to use read_poll_timeout() rather than open
coding that.

Patch 11 converts all printed messages to use the dev_*() functions so
the driver and devie name are always printed.

Patch 12 moves DW_VR_MII_DIG_CTRL1_2G5_EN to the correct place in the
header file, rather than amongst another register's definitions.

Patch 13 moves the Wangxun workaround to a common location rather than
duplicating it in two places. We also reformat this to fit within
80 columns.

====================

Tested-by: default avatarSerge Semin <fancer.lancer@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 36efaca9 bb0b8aec

drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c

+1 −1
Original line number Diff line number Diff line
@@ -451,7 +451,7 @@ static struct phylink_pcs *intel_mgbe_select_pcs(struct stmmac_priv *priv, 
	 * should always be an XPCS. The original code would always

	 * return this if present.

	 */

	return &priv->hw->xpcs->pcs;

	return xpcs_to_phylink_pcs(priv->hw->xpcs);

}



static int intel_mgbe_common_data(struct pci_dev *pdev,

drivers/net/pcs/pcs-xpcs-nxp.c

+8 −16
Original line number Diff line number Diff line
@@ -152,26 +152,18 @@ static int nxp_sja1110_pma_config(struct dw_xpcs *xpcs, 
	/* Enable TX and RX PLLs and circuits.

	 * Release reset of PMA to enable data flow to/from PCS.

	 */

	ret = xpcs_read(xpcs, MDIO_MMD_VEND2, SJA1110_POWERDOWN_ENABLE);

	if (ret < 0)

		return ret;



	val = ret & ~(SJA1110_TXPLL_PD | SJA1110_TXPD | SJA1110_RXCH_PD |

	ret = xpcs_modify(xpcs, MDIO_MMD_VEND2, SJA1110_POWERDOWN_ENABLE,

			  SJA1110_TXPLL_PD | SJA1110_TXPD | SJA1110_RXCH_PD |

			  SJA1110_RXBIAS_PD | SJA1110_RESET_SER_EN |

		      SJA1110_RESET_SER | SJA1110_RESET_DES);

	val |= SJA1110_RXPKDETEN | SJA1110_RCVEN;



	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_POWERDOWN_ENABLE, val);

			  SJA1110_RESET_SER | SJA1110_RESET_DES |

			  SJA1110_RXPKDETEN | SJA1110_RCVEN,

			  SJA1110_RXPKDETEN | SJA1110_RCVEN);

	if (ret < 0)

		return ret;



	/* Program continuous-time linear equalizer (CTLE) settings. */

	ret = xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RX_CDR_CTLE,

	return xpcs_write(xpcs, MDIO_MMD_VEND2, SJA1110_RX_CDR_CTLE,

			  rx_cdr_ctle);

	if (ret < 0)

		return ret;



	return 0;

}



int nxp_sja1110_sgmii_pma_config(struct dw_xpcs *xpcs)

drivers/net/pcs/pcs-xpcs-wx.c

+22 −34
Original line number Diff line number Diff line
@@ -46,25 +46,23 @@ 
#define TXGBE_VCO_CAL_LD0		0x72

#define TXGBE_VCO_CAL_REF0		0x76



static int txgbe_read_pma(struct dw_xpcs *xpcs, int reg)

static int txgbe_write_pma(struct dw_xpcs *xpcs, int reg, u16 val)

{

	return xpcs_read(xpcs, MDIO_MMD_PMAPMD, TXGBE_PMA_MMD + reg);

	return xpcs_write(xpcs, MDIO_MMD_PMAPMD, TXGBE_PMA_MMD + reg, val);

}



static int txgbe_write_pma(struct dw_xpcs *xpcs, int reg, u16 val)

static int txgbe_modify_pma(struct dw_xpcs *xpcs, int reg, u16 mask, u16 set)

{

	return xpcs_write(xpcs, MDIO_MMD_PMAPMD, TXGBE_PMA_MMD + reg, val);

	return xpcs_modify(xpcs, MDIO_MMD_PMAPMD, TXGBE_PMA_MMD + reg, mask,

			   set);

}



static void txgbe_pma_config_10gbaser(struct dw_xpcs *xpcs)

{

	int val;



	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL0, 0x21);

	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL3, 0);

	val = txgbe_read_pma(xpcs, TXGBE_TX_GENCTL1);

	val = u16_replace_bits(val, 0x5, TXGBE_TX_GENCTL1_VBOOST_LVL);

	txgbe_write_pma(xpcs, TXGBE_TX_GENCTL1, val);

	txgbe_modify_pma(xpcs, TXGBE_TX_GENCTL1, TXGBE_TX_GENCTL1_VBOOST_LVL,

			 FIELD_PREP(TXGBE_TX_GENCTL1_VBOOST_LVL, 0x5));

	txgbe_write_pma(xpcs, TXGBE_MISC_CTL0, TXGBE_MISC_CTL0_PLL |

			TXGBE_MISC_CTL0_CR_PARA_SEL | TXGBE_MISC_CTL0_RX_VREF(0xF));

	txgbe_write_pma(xpcs, TXGBE_VCO_CAL_LD0, 0x549);
@@ -78,38 +76,29 @@ static void txgbe_pma_config_10gbaser(struct dw_xpcs *xpcs) 


	txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL0, TXGBE_RX_EQ_CTL0_CTLE_POLE(2) |

			TXGBE_RX_EQ_CTL0_CTLE_BOOST(5));

	val = txgbe_read_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL);

	val &= ~TXGBE_RX_EQ_ATTN_LVL0;

	txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val);

	txgbe_modify_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, TXGBE_RX_EQ_ATTN_LVL0, 0);

	txgbe_write_pma(xpcs, TXGBE_DFE_TAP_CTL0, 0xBE);

	val = txgbe_read_pma(xpcs, TXGBE_AFE_DFE_ENABLE);

	val &= ~(TXGBE_DFE_EN_0 | TXGBE_AFE_EN_0);

	txgbe_write_pma(xpcs, TXGBE_AFE_DFE_ENABLE, val);

	val = txgbe_read_pma(xpcs, TXGBE_RX_EQ_CTL4);

	val &= ~TXGBE_RX_EQ_CTL4_CONT_ADAPT0;

	txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL4, val);

	txgbe_modify_pma(xpcs, TXGBE_AFE_DFE_ENABLE,

			 TXGBE_DFE_EN_0 | TXGBE_AFE_EN_0, 0);

	txgbe_modify_pma(xpcs, TXGBE_RX_EQ_CTL4, TXGBE_RX_EQ_CTL4_CONT_ADAPT0,

			 0);

}



static void txgbe_pma_config_1g(struct dw_xpcs *xpcs)

{

	int val;



	val = txgbe_read_pma(xpcs, TXGBE_TX_GENCTL1);

	val = u16_replace_bits(val, 0x5, TXGBE_TX_GENCTL1_VBOOST_LVL);

	val &= ~TXGBE_TX_GENCTL1_VBOOST_EN0;

	txgbe_write_pma(xpcs, TXGBE_TX_GENCTL1, val);

	txgbe_modify_pma(xpcs, TXGBE_TX_GENCTL1,

			 TXGBE_TX_GENCTL1_VBOOST_LVL |

			 TXGBE_TX_GENCTL1_VBOOST_EN0,

			 FIELD_PREP(TXGBE_TX_GENCTL1_VBOOST_LVL, 0x5));

	txgbe_write_pma(xpcs, TXGBE_MISC_CTL0, TXGBE_MISC_CTL0_PLL |

			TXGBE_MISC_CTL0_CR_PARA_SEL | TXGBE_MISC_CTL0_RX_VREF(0xF));



	txgbe_write_pma(xpcs, TXGBE_RX_EQ_CTL0, TXGBE_RX_EQ_CTL0_VGA1_GAIN(7) |

			TXGBE_RX_EQ_CTL0_VGA2_GAIN(7) | TXGBE_RX_EQ_CTL0_CTLE_BOOST(6));

	val = txgbe_read_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL);

	val &= ~TXGBE_RX_EQ_ATTN_LVL0;

	txgbe_write_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, val);

	txgbe_modify_pma(xpcs, TXGBE_RX_EQ_ATTN_CTL, TXGBE_RX_EQ_ATTN_LVL0, 0);

	txgbe_write_pma(xpcs, TXGBE_DFE_TAP_CTL0, 0);

	val = txgbe_read_pma(xpcs, TXGBE_RX_GEN_CTL3);

	val = u16_replace_bits(val, 0x4, TXGBE_RX_GEN_CTL3_LOS_TRSHLD0);

	txgbe_write_pma(xpcs, TXGBE_RX_GEN_CTL3, val);

	txgbe_modify_pma(xpcs, TXGBE_RX_GEN_CTL3, TXGBE_RX_GEN_CTL3_LOS_TRSHLD0,

			 FIELD_PREP(TXGBE_RX_GEN_CTL3_LOS_TRSHLD0, 0x4));



	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL0, 0x20);

	txgbe_write_pma(xpcs, TXGBE_MPLLA_CTL3, 0x46);
@@ -172,7 +161,7 @@ static bool txgbe_xpcs_mode_quirk(struct dw_xpcs *xpcs) 


int txgbe_xpcs_switch_mode(struct dw_xpcs *xpcs, phy_interface_t interface)

{

	int val, ret;

	int ret;



	switch (interface) {

	case PHY_INTERFACE_MODE_10GBASER:
@@ -194,9 +183,8 @@ int txgbe_xpcs_switch_mode(struct dw_xpcs *xpcs, phy_interface_t interface) 


	if (interface == PHY_INTERFACE_MODE_10GBASER) {

		xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL2, MDIO_PCS_CTRL2_10GBR);

		val = xpcs_read(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1);

		val |= MDIO_CTRL1_SPEED10G;

		xpcs_write(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1, val);

		xpcs_modify(xpcs, MDIO_MMD_PMAPMD, MDIO_CTRL1,

			    MDIO_CTRL1_SPEED10G, MDIO_CTRL1_SPEED10G);

		txgbe_pma_config_10gbaser(xpcs);

	} else {

		xpcs_write(xpcs, MDIO_MMD_PCS, MDIO_CTRL2, MDIO_PCS_CTRL2_10GBX);

drivers/net/pcs/pcs-xpcs.c

+184 −261

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drivers/net/pcs/pcs-xpcs.h

+20 −6

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