Commit f3271893 authored by Sung Joon Kim's avatar Sung Joon Kim Committed by Alex Deucher
Browse files

drm/amd/display: Support UHBR10 link rate on eDP 



[why]
Supporting UHBR10 link rate on eDP leverages
the existing DP2.0 code but need to add some small
adjustments in code.

[how]
Acknowledge the given DPCD caps for UHBR10
link rate support and allow DP2.0 programming
sequence and link training for eDP.

Reviewed-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Signed-off-by: default avatarSung Joon Kim <Sungjoon.Kim@amd.com>
Signed-off-by: default avatarRoman Li <roman.li@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 272e6aab

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -1760,6 +1760,7 @@ struct dc_link { 
		bool dongle_mode_timing_override;

		bool blank_stream_on_ocs_change;

		bool read_dpcd204h_on_irq_hpd;

		bool disable_assr_for_uhbr;

	} wa_flags;

	struct link_mst_stream_allocation_table mst_stream_alloc_table;

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

+12 −11
Original line number Diff line number Diff line
@@ -1232,8 +1232,11 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx) 
			 * has changed or they enter protection state and hang.

			 */

			msleep(60);

		} else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {

			if (!link->dc->config.edp_no_power_sequencing) {

		}

	}



	if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&

	    !link->dc->config.edp_no_power_sequencing) {

			/*

			 * Sometimes, DP receiver chip power-controlled externally by an

			 * Embedded Controller could be treated and used as eDP,
@@ -1243,8 +1246,6 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx) 
			 */

		link->dc->link_srv->edp_receiver_ready_T9(link);

	}

		}

	}



}

drivers/gpu/drm/amd/display/dc/link/link_dpms.c

+2 −2
Original line number Diff line number Diff line
@@ -2358,7 +2358,7 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx) 


	if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

		deallocate_mst_payload(pipe_ctx);

	else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&

	else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) &&

			dp_is_128b_132b_signal(pipe_ctx))

		update_sst_payload(pipe_ctx, false);
@@ -2591,7 +2591,7 @@ void link_set_dpms_on( 


	if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)

		allocate_mst_payload(pipe_ctx);

	else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT &&

	else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) &&

			dp_is_128b_132b_signal(pipe_ctx))

		update_sst_payload(pipe_ctx, true);

drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c

+3 −0
Original line number Diff line number Diff line
@@ -1168,6 +1168,9 @@ static void edp_set_assr_enable(const struct dc *pDC, struct dc_link *link, 
	link_enc_index = link->link_enc->transmitter - TRANSMITTER_UNIPHY_A;



	if (link_res->hpo_dp_link_enc) {

		if (link->wa_flags.disable_assr_for_uhbr)

			return;



		link_enc_index = link_res->hpo_dp_link_enc->inst;

		use_hpo_dp_link_enc = true;

	}