Commit f3a1d69f authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-next-6.19-2025-11-14' of... 

Merge tag 'amd-drm-next-6.19-2025-11-14' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-next

amd-drm-next-6.19-2025-11-14:

amdgpu:
- RAS updates
- GC12 DCC P2P fix
- Documentation fixes
- Power limit code cleanup
- Userq updates
- VRR fix
- SMART OLED support
- DSC refactor for DCN 3.5
- Replay updates
- DC clockgating updates
- HDCP refactor
- ISP fix
- SMU 13.0.12 updates
- JPEG 5.0.1 fix
- VCE1 support
- Enable DC by default on SI
- Refactor CIK and SI enablement
- Enable amdgpu by default for CI dGPUs
- XGMI fixes
- SR-IOV fixes
- Memory allocation critical path fixes
- Enable amdgpu by default on SI dGPUs

amdkfd:
- Relax checks on save area overallocations
- Fix GPU mappings after prefetch

radeon:
- Refactor CIK and SI enablement

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patch.msgid.link/20251114192553.442621-1-alexander.deucher@amd.com
parents fd1a11ea ccd3b4c7

drivers/gpu/drm/amd/amdgpu/Kconfig

+16 −8
Original line number Diff line number Diff line
@@ -43,14 +43,16 @@ config DRM_AMDGPU_SI 
	bool "Enable amdgpu support for SI parts"

	depends on DRM_AMDGPU

	help

	  Choose this option if you want to enable experimental support

	  Choose this option if you want to enable support

	  for SI (Southern Islands) asics.



	  SI is already supported in radeon. Experimental support for SI

	  in amdgpu will be disabled by default and is still provided by

	  radeon. Use module options to override this:

	  SI (Southern Islands) are first generation GCN GPUs,

	  supported by both drivers: radeon (old) and amdgpu (new).

	  By default, SI dedicated GPUs are supported by amdgpu.



	  radeon.si_support=0 amdgpu.si_support=1

	  Use module options to override this:

	  To use radeon for SI,

	  radeon.si_support=1 amdgpu.si_support=0



config DRM_AMDGPU_CIK

	bool "Enable amdgpu support for CIK parts"
@@ -59,11 +61,17 @@ config DRM_AMDGPU_CIK 
	  Choose this option if you want to enable support for CIK (Sea

	  Islands) asics.



	  CIK is already supported in radeon. Support for CIK in amdgpu

	  will be disabled by default and is still provided by radeon.

	  Use module options to override this:

	  CIK (Sea Islands) are second generation GCN GPUs,

	  supported by both drivers: radeon (old) and amdgpu (new).

	  By default,

	  CIK dedicated GPUs are supported by amdgpu

	  CIK APUs are supported by radeon



	  Use module options to override this:

	  To use amdgpu for CIK,

	  radeon.cik_support=0 amdgpu.cik_support=1

	  To use radeon for CIK,

	  radeon.cik_support=1 amdgpu.cik_support=0



config DRM_AMDGPU_USERPTR

	bool "Always enable userptr write support"

drivers/gpu/drm/amd/amdgpu/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -78,7 +78,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o \ 
	dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o



amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o \

	uvd_v3_1.o

	uvd_v3_1.o vce_v1_0.o



amdgpu-y += \

	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+0 −15
Original line number Diff line number Diff line
@@ -36,7 +36,6 @@ 
#include "amdgpu_ras.h"

#include "amdgpu_umc.h"

#include "amdgpu_reset.h"

#include "amdgpu_ras_mgr.h"



/* Total memory size in system memory and all GPU VRAM. Used to

 * estimate worst case amount of memory to reserve for page tables
@@ -747,20 +746,6 @@ void amdgpu_amdkfd_ras_pasid_poison_consumption_handler(struct amdgpu_device *ad 
				enum amdgpu_ras_block block, uint16_t pasid,

				pasid_notify pasid_fn, void *data, uint32_t reset)

{



	if (amdgpu_uniras_enabled(adev)) {

		struct ras_ih_info ih_info;



		memset(&ih_info, 0, sizeof(ih_info));

		ih_info.block = block;

		ih_info.pasid = pasid;

		ih_info.reset = reset;

		ih_info.pasid_fn = pasid_fn;

		ih_info.data = data;

		amdgpu_ras_mgr_handle_consumer_interrupt(adev, &ih_info);

		return;

	}



	amdgpu_umc_pasid_poison_handler(adev, block, pasid, pasid_fn, data, reset);

}

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

+1 −1
Original line number Diff line number Diff line
@@ -236,7 +236,7 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, 
		r = amdgpu_xcp_select_scheds(adev, hw_ip, hw_prio, fpriv,

						&num_scheds, &scheds);

		if (r)

			goto cleanup_entity;

			goto error_free_entity;

	}



	/* disable load balance if the hw engine retains context among dependent jobs */

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+2 −13
Original line number Diff line number Diff line
@@ -4249,24 +4249,13 @@ bool amdgpu_device_asic_has_dc_support(struct pci_dev *pdev, 
	case CHIP_PITCAIRN:

	case CHIP_VERDE:

	case CHIP_OLAND:

		/*

		 * We have systems in the wild with these ASICs that require

		 * LVDS and VGA support which is not supported with DC.

		 *

		 * Fallback to the non-DC driver here by default so as not to

		 * cause regressions.

		 */

#if defined(CONFIG_DRM_AMD_DC_SI)

		return amdgpu_dc > 0;

#else

		return false;

#endif

		return amdgpu_dc != 0 && IS_ENABLED(CONFIG_DRM_AMD_DC_SI);

	case CHIP_KAVERI:

	case CHIP_KABINI:

	case CHIP_MULLINS:

		/*

		 * We have systems in the wild with these ASICs that require

		 * VGA support which is not supported with DC.

		 * TRAVIS and NUTMEG support which is not supported with DC.

		 *

		 * Fallback to the non-DC driver here by default so as not to

		 * cause regressions.