Unverified Commit f3bfa0f0 authored by J. Neuschäfer's avatar J. Neuschäfer Committed by Mark Brown
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spi: dt-bindings: Convert Freescale SPI bindings to YAML 



fsl-spi.txt contains the bindings for the fsl,spi and fsl,espi
contollers. Convert them to YAML.

Reviewed-by: default avatar"Rob Herring (Arm)" <robh@kernel.org>
Signed-off-by: default avatarJ. Neuschäfer <j.ne@posteo.net>
Link: https://patch.msgid.link/20250220-ppcyaml-spi-v3-1-e340613c7875@posteo.net


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent cb15abd4

Documentation/devicetree/bindings/spi/fsl,espi.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/fsl,espi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale eSPI (Enhanced Serial Peripheral Interface) controller



maintainers:

  - J. Neuschäfer <j.ne@posteo.net>



properties:

  compatible:

    const: fsl,mpc8536-espi



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  fsl,espi-num-chipselects:

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [ 1, 4 ]

    description: The number of the chipselect signals.



  fsl,csbef:

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 0

    maximum: 15

    description: Chip select assertion time in bits before frame starts



  fsl,csaft:

    $ref: /schemas/types.yaml#/definitions/uint32

    minimum: 0

    maximum: 15

    description: Chip select negation time in bits after frame ends



required:

  - compatible

  - reg

  - interrupts

  - fsl,espi-num-chipselects



allOf:

  - $ref: spi-controller.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>



    spi@110000 {

        compatible = "fsl,mpc8536-espi";

        reg = <0x110000 0x1000>;

        #address-cells = <1>;

        #size-cells = <0>;

        interrupts = <53 IRQ_TYPE_EDGE_FALLING>;

        fsl,espi-num-chipselects = <4>;

        fsl,csbef = <1>;

        fsl,csaft = <1>;

    };



...

Documentation/devicetree/bindings/spi/fsl,spi.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/fsl,spi.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Freescale SPI (Serial Peripheral Interface) controller



maintainers:

  - J. Neuschäfer <j.ne@posteo.net>



properties:

  compatible:

    enum:

      - fsl,spi

      - aeroflexgaisler,spictrl



  reg:

    maxItems: 1



  cell-index:

    $ref: /schemas/types.yaml#/definitions/uint32

    description: |

      QE SPI subblock index.

      0: QE subblock SPI1

      1: QE subblock SPI2



  mode:

    description: SPI operation mode

    enum:

      - cpu

      - cpu-qe



  interrupts:

    maxItems: 1



  clock-frequency:

    description: input clock frequency to non FSL_SOC cores



  cs-gpios: true



  fsl,spisel_boot:

    $ref: /schemas/types.yaml#/definitions/flag

    description:

      For the MPC8306 and MPC8309, specifies that the SPISEL_BOOT signal is used

      as chip select for a slave device. Use reg = <number of gpios> in the

      corresponding child node, i.e. 0 if the cs-gpios property is not present.



required:

  - compatible

  - reg

  - mode

  - interrupts



allOf:

  - $ref: spi-controller.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>



    spi@4c0 {

        compatible = "fsl,spi";

        reg = <0x4c0 0x40>;

        cell-index = <0>;

        interrupts = <82 0>;

        mode = "cpu";

        cs-gpios = <&gpio 18 IRQ_TYPE_EDGE_RISING          // device reg=<0>

                    &gpio 19 IRQ_TYPE_EDGE_RISING>;        // device reg=<1>

    };



...

Documentation/devicetree/bindings/spi/fsl-spi.txt

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* SPI (Serial Peripheral Interface)



Required properties:

- cell-index : QE SPI subblock index.

		0: QE subblock SPI1

		1: QE subblock SPI2

- compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl".

- mode : the SPI operation mode, it can be "cpu" or "cpu-qe".

- reg : Offset and length of the register set for the device

- interrupts : <a b> where a is the interrupt number and b is a

  field that represents an encoding of the sense and level

  information for the interrupt.  This should be encoded based on

  the information in section 2) depending on the type of interrupt

  controller you have.

- clock-frequency : input clock frequency to non FSL_SOC cores



Optional properties:

- cs-gpios : specifies the gpio pins to be used for chipselects.

  The gpios will be referred to as reg = <index> in the SPI child nodes.

  If unspecified, a single SPI device without a chip select can be used.

- fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the

  SPISEL_BOOT signal is used as chip select for a slave device. Use

  reg = <number of gpios> in the corresponding child node, i.e. 0 if

  the cs-gpios property is not present.



Example:

	spi@4c0 {

		cell-index = <0>;

		compatible = "fsl,spi";

		reg = <4c0 40>;

		interrupts = <82 0>;

		interrupt-parent = <700>;

		mode = "cpu";

		cs-gpios = <&gpio 18 1		// device reg=<0>

			    &gpio 19 1>;	// device reg=<1>

	};





* eSPI (Enhanced Serial Peripheral Interface)



Required properties:

- compatible : should be "fsl,mpc8536-espi".

- reg : Offset and length of the register set for the device.

- interrupts : should contain eSPI interrupt, the device has one interrupt.

- fsl,espi-num-chipselects : the number of the chipselect signals.



Optional properties:

- fsl,csbef: chip select assertion time in bits before frame starts

- fsl,csaft: chip select negation time in bits after frame ends



Example:

	spi@110000 {

		#address-cells = <1>;

		#size-cells = <0>;

		compatible = "fsl,mpc8536-espi";

		reg = <0x110000 0x1000>;

		interrupts = <53 0x2>;

		interrupt-parent = <&mpic>;

		fsl,espi-num-chipselects = <4>;

		fsl,csbef = <1>;

		fsl,csaft = <1>;

	};