Commit f3c19e70 authored by Bartosz Golaszewski's avatar Bartosz Golaszewski
Browse files

gpio: mlxbf3: use new generic GPIO chip API 



Convert the driver to using the new generic GPIO chip interfaces from
linux/gpio/generic.h.

Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20250903-gpio-mmio-gpio-conv-part3-v1-12-ff346509f408@linaro.org


Signed-off-by: default avatarBartosz Golaszewski <bartosz.golaszewski@linaro.org>
parent ab61c8b6

drivers/gpio/gpio-mlxbf3.c

+53 −50
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
#include <linux/device.h>

#include <linux/err.h>

#include <linux/gpio/driver.h>

#include <linux/gpio/generic.h>

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/module.h>
@@ -42,7 +43,7 @@ 
#define MLXBF_GPIO_CLR_ALL_INTS           GENMASK(31, 0)



struct mlxbf3_gpio_context {

	struct gpio_chip gc;

	struct gpio_generic_chip chip;



	/* YU GPIO block address */

	void __iomem *gpio_set_io;
@@ -58,18 +59,17 @@ static void mlxbf3_gpio_irq_enable(struct irq_data *irqd) 
	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);

	struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);

	irq_hw_number_t offset = irqd_to_hwirq(irqd);

	unsigned long flags;

	u32 val;



	gpiochip_enable_irq(gc, offset);



	raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);

	guard(gpio_generic_lock_irqsave)(&gs->chip);



	writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);



	val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);

	val |= BIT(offset);

	writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);

	raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);

}



static void mlxbf3_gpio_irq_disable(struct irq_data *irqd)
@@ -77,16 +77,15 @@ static void mlxbf3_gpio_irq_disable(struct irq_data *irqd) 
	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);

	struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);

	irq_hw_number_t offset = irqd_to_hwirq(irqd);

	unsigned long flags;

	u32 val;



	raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);

	scoped_guard(gpio_generic_lock_irqsave, &gs->chip) {

		val = readl(gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);

		val &= ~BIT(offset);

		writel(val, gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_EVTEN0);



		writel(BIT(offset), gs->gpio_cause_io + MLXBF_GPIO_CAUSE_OR_CLRCAUSE);

	raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);

	}



	gpiochip_disable_irq(gc, offset);

}
@@ -94,7 +93,7 @@ static void mlxbf3_gpio_irq_disable(struct irq_data *irqd) 
static irqreturn_t mlxbf3_gpio_irq_handler(int irq, void *ptr)

{

	struct mlxbf3_gpio_context *gs = ptr;

	struct gpio_chip *gc = &gs->gc;

	struct gpio_chip *gc = &gs->chip.gc;

	unsigned long pending;

	u32 level;
@@ -113,11 +112,9 @@ mlxbf3_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) 
	struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);

	struct mlxbf3_gpio_context *gs = gpiochip_get_data(gc);

	irq_hw_number_t offset = irqd_to_hwirq(irqd);

	unsigned long flags;

	u32 val;



	raw_spin_lock_irqsave(&gs->gc.bgpio_lock, flags);



	scoped_guard(gpio_generic_lock_irqsave, &gs->chip) {

		switch (type & IRQ_TYPE_SENSE_MASK) {

		case IRQ_TYPE_EDGE_BOTH:

			val = readl(gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);
@@ -138,11 +135,9 @@ mlxbf3_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) 
			writel(val, gs->gpio_io + MLXBF_GPIO_CAUSE_FALL_EN);

			break;

		default:

		raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);

			return -EINVAL;

		}



	raw_spin_unlock_irqrestore(&gs->gc.bgpio_lock, flags);

	}



	irq_set_handler_locked(irqd, handle_edge_irq);
@@ -186,6 +181,7 @@ static int mlxbf3_gpio_add_pin_ranges(struct gpio_chip *chip) 


static int mlxbf3_gpio_probe(struct platform_device *pdev)

{

	struct gpio_generic_chip_config config;

	struct device *dev = &pdev->dev;

	struct mlxbf3_gpio_context *gs;

	struct gpio_irq_chip *girq;
@@ -211,16 +207,23 @@ static int mlxbf3_gpio_probe(struct platform_device *pdev) 
	gs->gpio_clr_io = devm_platform_ioremap_resource(pdev, 3);

	if (IS_ERR(gs->gpio_clr_io))

		return PTR_ERR(gs->gpio_clr_io);

	gc = &gs->gc;



	ret = bgpio_init(gc, dev, 4,

			gs->gpio_io + MLXBF_GPIO_READ_DATA_IN,

			gs->gpio_set_io + MLXBF_GPIO_FW_DATA_OUT_SET,

			gs->gpio_clr_io + MLXBF_GPIO_FW_DATA_OUT_CLEAR,

			gs->gpio_set_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_SET,

			gs->gpio_clr_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR, 0);

	gc = &gs->chip.gc;



	config = (typeof(config)){

		.dev = dev,

		.sz = 4,

		.dat = gs->gpio_io + MLXBF_GPIO_READ_DATA_IN,

		.set = gs->gpio_set_io + MLXBF_GPIO_FW_DATA_OUT_SET,

		.clr = gs->gpio_clr_io + MLXBF_GPIO_FW_DATA_OUT_CLEAR,

		.dirout = gs->gpio_set_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_SET,

		.dirin = gs->gpio_clr_io + MLXBF_GPIO_FW_OUTPUT_ENABLE_CLEAR,

	};



	ret = gpio_generic_chip_init(&gs->chip, &config);

	if (ret)

		return dev_err_probe(dev, ret, "%s: bgpio_init() failed", __func__);

		return dev_err_probe(dev, ret,

				     "%s: failed to initialize the generic GPIO chip",

				     __func__);



	gc->request = gpiochip_generic_request;

	gc->free = gpiochip_generic_free;
@@ -229,7 +232,7 @@ static int mlxbf3_gpio_probe(struct platform_device *pdev) 


	irq = platform_get_irq_optional(pdev, 0);

	if (irq >= 0) {

		girq = &gs->gc.irq;

		girq = &gs->chip.gc.irq;

		gpio_irq_chip_set_chip(girq, &gpio_mlxbf3_irqchip);

		girq->default_type = IRQ_TYPE_NONE;

		/* This will let us handle the parent IRQ in the driver */
@@ -250,7 +253,7 @@ static int mlxbf3_gpio_probe(struct platform_device *pdev) 


	platform_set_drvdata(pdev, gs);



	ret = devm_gpiochip_add_data(dev, &gs->gc, gs);

	ret = devm_gpiochip_add_data(dev, gc, gs);

	if (ret)

		dev_err_probe(dev, ret, "Failed adding memory mapped gpiochip\n");