Commit f3c1d372 authored by Jason Gunthorpe's avatar Jason Gunthorpe Committed by Will Deacon
Browse files

iommu/arm-smmu-v3: Mark STE MEV safe when computing the update sequence 



Nested CD tables set the MEV bit to try to reduce multi-fault spamming on
the hypervisor. Since MEV is in STE word 1 this causes a breaking update
sequence that is not required and impacts real workloads.

For the purposes of STE updates the value of MEV doesn't matter, if it is
set/cleared early or late it just results in a change to the fault reports
that must be supported by the kernel anyhow. The spec says:

 Note: Software must expect, and be able to deal with, coalesced fault
 records even when MEV == 0.

So mark STE MEV safe when computing the update sequence, to avoid creating
a breaking update.

Fixes: da0c5652 ("iommu/arm-smmu-v3: Set MEV bit in nested STE for DoS mitigations")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Reviewed-by: default avatarShuai Xue <xueshuai@linux.alibaba.com>
Reviewed-by: default avatarMostafa Saleh <smostafa@google.com>
Reviewed-by: default avatarPranjal Shrivastava <praan@google.com>
Signed-off-by: default avatarNicolin Chen <nicolinc@nvidia.com>
Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 2781f2a9

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

+10 −0
Original line number Diff line number Diff line
@@ -1097,6 +1097,16 @@ VISIBLE_IF_KUNIT 
void arm_smmu_get_ste_update_safe(const __le64 *cur, const __le64 *target,

				  __le64 *safe_bits)

{

	/*

	 * MEV does not meaningfully impact the operation of the HW, it only

	 * changes how many fault events are generated, thus we can relax it

	 * when computing the ordering. The spec notes the device can act like

	 * MEV=1 anyhow:

	 *

	 *  Note: Software must expect, and be able to deal with, coalesced

	 *  fault records even when MEV == 0.

	 */

	safe_bits[1] |= cpu_to_le64(STRTAB_STE_1_MEV);

}

EXPORT_SYMBOL_IF_KUNIT(arm_smmu_get_ste_update_safe);