Commit f459672c authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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arm64: dts: renesas: r9a09g087: Fix CPG register region sizes 



The CPG register regions were incorrectly sized.  Update them to match
the actual hardware specification:
  - First region (0x80280000): 0x1000 -> 0x10000 (64kiB)
  - Second region (0x81280000): 0x9000 -> 0x10000 (64kiB)

Fixes: 4b3d31f0 ("arm64: dts: renesas: Add initial SoC DTSI for the RZ/N2H SoC")
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260213131742.3606334-3-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent b12985ce

arch/arm64/boot/dts/renesas/r9a09g087.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -977,8 +977,8 @@ mii_conv3: mii-conv@3 { 


		cpg: clock-controller@80280000 {

			compatible = "renesas,r9a09g087-cpg-mssr";

			reg = <0 0x80280000 0 0x1000>,

			      <0 0x81280000 0 0x9000>;

			reg = <0 0x80280000 0 0x10000>,

			      <0 0x81280000 0 0x10000>;

			clocks = <&extal_clk>;

			clock-names = "extal";

			#clock-cells = <2>;