Commit f45b2949 authored by Paul Kocialkowski's avatar Paul Kocialkowski Committed by Chen-Yu Tsai
Browse files

clk: sunxi-ng: v3s: Fix CSI SCLK clock name 



The CSI SCLK clock is incorrectly called CSI1 SCLK while it is used for
both the CSI0 and CSI1 interfaces and is called CSI SCLK all around the
documentation.

Fix the name in the driver, header and device-tree.

Fixes: d0f11d14 ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: default avatarPaul Kocialkowski <paulk@sys-base.io>
Reviewed-By: default avatarIcenowy Zheng <uwu@icenowy.me>
Link: https://patch.msgid.link/20250701201124.812882-3-paulk@sys-base.io


Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
parent 713d4887

Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml

+1 −1
Original line number Diff line number Diff line
@@ -110,7 +110,7 @@ examples: 
        reg = <0x01cb4000 0x1000>;

        interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&ccu CLK_BUS_CSI>,

                 <&ccu CLK_CSI1_SCLK>,

                 <&ccu CLK_CSI_SCLK>,

                 <&ccu CLK_DRAM_CSI>;

        clock-names = "bus",

                      "mod",

Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml

+1 −1
Original line number Diff line number Diff line
@@ -79,7 +79,7 @@ examples: 
        reg = <0x01cb8000 0x1000>;

        interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&ccu CLK_BUS_CSI>,

             <&ccu CLK_CSI1_SCLK>,

             <&ccu CLK_CSI_SCLK>,

             <&ccu CLK_DRAM_CSI>;

        clock-names = "bus", "mod", "ram";

        resets = <&ccu RST_BUS_CSI>;

Documentation/devicetree/bindings/media/allwinner,sun6i-a31-mipi-csi2.yaml

+1 −1
Original line number Diff line number Diff line
@@ -103,7 +103,7 @@ examples: 
        reg = <0x01cb1000 0x1000>;

        interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&ccu CLK_BUS_CSI>,

                 <&ccu CLK_CSI1_SCLK>;

                 <&ccu CLK_CSI_SCLK>;

        clock-names = "bus", "mod";

        resets = <&ccu RST_BUS_CSI>;

arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -652,7 +652,7 @@ csi1: camera@1cb4000 { 
			reg = <0x01cb4000 0x3000>;

			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&ccu CLK_BUS_CSI>,

				 <&ccu CLK_CSI1_SCLK>,

				 <&ccu CLK_CSI_SCLK>,

				 <&ccu CLK_DRAM_CSI>;

			clock-names = "bus", "mod", "ram";

			resets = <&ccu RST_BUS_CSI>;

drivers/clk/sunxi-ng/ccu-sun8i-v3s.c

+5 −5
Original line number Diff line number Diff line
@@ -362,8 +362,8 @@ static const char * const csi_mclk_parents[] = { "osc24M", "pll-video", 
static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,

				 0x130, 0, 5, 8, 3, BIT(15), 0);



static const char * const csi1_sclk_parents[] = { "pll-video", "pll-isp" };

static SUNXI_CCU_M_WITH_MUX_GATE(csi1_sclk_clk, "csi-sclk", csi1_sclk_parents,

static const char * const csi_sclk_parents[] = { "pll-video", "pll-isp" };

static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk", csi_sclk_parents,

				 0x134, 16, 4, 24, 3, BIT(31), 0);



static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi-mclk", csi_mclk_parents,
@@ -452,7 +452,7 @@ static struct ccu_common *sun8i_v3s_ccu_clks[] = { 
	&tcon_clk.common,

	&csi_misc_clk.common,

	&csi0_mclk_clk.common,

	&csi1_sclk_clk.common,

	&csi_sclk_clk.common,

	&csi1_mclk_clk.common,

	&ve_clk.common,

	&ac_dig_clk.common,
@@ -551,7 +551,7 @@ static struct clk_hw_onecell_data sun8i_v3s_hw_clks = { 
		[CLK_TCON0]		= &tcon_clk.common.hw,

		[CLK_CSI_MISC]		= &csi_misc_clk.common.hw,

		[CLK_CSI0_MCLK]		= &csi0_mclk_clk.common.hw,

		[CLK_CSI1_SCLK]		= &csi1_sclk_clk.common.hw,

		[CLK_CSI_SCLK]		= &csi_sclk_clk.common.hw,

		[CLK_CSI1_MCLK]		= &csi1_mclk_clk.common.hw,

		[CLK_VE]		= &ve_clk.common.hw,

		[CLK_AC_DIG]		= &ac_dig_clk.common.hw,
@@ -633,7 +633,7 @@ static struct clk_hw_onecell_data sun8i_v3_hw_clks = { 
		[CLK_TCON0]		= &tcon_clk.common.hw,

		[CLK_CSI_MISC]		= &csi_misc_clk.common.hw,

		[CLK_CSI0_MCLK]		= &csi0_mclk_clk.common.hw,

		[CLK_CSI1_SCLK]		= &csi1_sclk_clk.common.hw,

		[CLK_CSI_SCLK]		= &csi_sclk_clk.common.hw,

		[CLK_CSI1_MCLK]		= &csi1_mclk_clk.common.hw,

		[CLK_VE]		= &ve_clk.common.hw,

		[CLK_AC_DIG]		= &ac_dig_clk.common.hw,