Unverified Commit f46c06a3 authored by Stephen Boyd's avatar Stephen Boyd
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Merge tag 'clk-imx-6.17' of... 

Merge tag 'clk-imx-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx

Pull i.MX clk driver updates from Abel Vesa:

 - Document bindings for i.MX94 LVDS/Display CSR
 - Fix synchronous abort in i.MX95 BLK CTL driver
 - Rename LVDS and displaymix CSR BLK needed for supporting i.MX943
 - Add i.MX94 LVDS/Display CSR clock to the i.MX95 BLK CTL
 - Update MAINTAINERS entry to include both nxp,imx* and fsl,imx*

* tag 'clk-imx-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
  MAINTAINERS: Update i.MX Clock Entry
  clk: imx95-blk-ctl: Add clock for i.MX94 LVDS/Display CSR
  clk: imx95-blk-ctl: Rename lvds and displaymix csr blk
  clk: imx95-blk-ctl: Fix synchronous abort
  dt-bindings: clock: Add support for i.MX94 LVDS/DISPLAY CSR
  clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_data
parents 19272b37 c7886524

Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml

+2 −0
Original line number Diff line number Diff line
@@ -13,6 +13,8 @@ properties: 
  compatible:

    items:

      - enum:

          - nxp,imx94-display-csr

          - nxp,imx94-lvds-csr

          - nxp,imx95-camera-csr

          - nxp,imx95-display-csr

          - nxp,imx95-hsio-blk-ctl

MAINTAINERS

+2 −2
Original line number Diff line number Diff line
@@ -17951,9 +17951,9 @@ L: linux-clk@vger.kernel.org 
L:	imx@lists.linux.dev

S:	Maintained

T:	git git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux.git clk/imx

F:	Documentation/devicetree/bindings/clock/imx*

F:	Documentation/devicetree/bindings/clock/*imx*

F:	drivers/clk/imx/

F:	include/dt-bindings/clock/imx*

F:	include/dt-bindings/clock/*imx*









NXP PF8100/PF8121A/PF8200 PMIC REGULATOR DEVICE DRIVER









M:	Jagan Teki <jagan@amarulasolutions.com>

























drivers/clk/imx/clk-imx95-blk-ctl.c



+74
−21






























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// SPDX-License-Identifier: GPL-2.0









/*









 * Copyright 2024 NXP









 * Copyright 2024-2025 NXP









 */



















#include <dt-bindings/clock/nxp,imx94-clock.h>









#include <dt-bindings/clock/nxp,imx95-clock.h>









#include <linux/clk.h>









#include <linux/clk-provider.h>








@@ -156,7 +157,7 @@ static const struct imx95_blk_ctl_dev_data camblk_dev_data = {







	.clk_reg_offset = 0,









};



















static const struct imx95_blk_ctl_clk_dev_data lvds_clk_dev_data[] = {









static const struct imx95_blk_ctl_clk_dev_data imx95_lvds_clk_dev_data[] = {









	[IMX95_CLK_DISPMIX_LVDS_PHY_DIV] = {









		.name = "ldb_phy_div",









		.parent_names = (const char *[]){ "ldbpll", },








@@ -213,17 +214,21 @@ static const struct imx95_blk_ctl_clk_dev_data lvds_clk_dev_data[] = {







	},









};



















static const struct imx95_blk_ctl_dev_data lvds_csr_dev_data = {









	.num_clks = ARRAY_SIZE(lvds_clk_dev_data),









	.clk_dev_data = lvds_clk_dev_data,









static const struct imx95_blk_ctl_dev_data imx95_lvds_csr_dev_data = {









	.num_clks = ARRAY_SIZE(imx95_lvds_clk_dev_data),









	.clk_dev_data = imx95_lvds_clk_dev_data,









	.clk_reg_offset = 0,









};



















static const struct imx95_blk_ctl_clk_dev_data dispmix_csr_clk_dev_data[] = {









static const char * const imx95_disp_engine_parents[] = {









	"videopll1", "dsi_pll", "ldb_pll_div7"









};



















static const struct imx95_blk_ctl_clk_dev_data imx95_dispmix_csr_clk_dev_data[] = {









	[IMX95_CLK_DISPMIX_ENG0_SEL] = {









		.name = "disp_engine0_sel",









		.parent_names = (const char *[]){"videopll1", "dsi_pll", "ldb_pll_div7", },









		.num_parents = 4,









		.parent_names = imx95_disp_engine_parents,









		.num_parents = ARRAY_SIZE(imx95_disp_engine_parents),









		.reg = 0,









		.bit_idx = 0,









		.bit_width = 2,








@@ -232,8 +237,8 @@ static const struct imx95_blk_ctl_clk_dev_data dispmix_csr_clk_dev_data[] = {







	},









	[IMX95_CLK_DISPMIX_ENG1_SEL] = {









		.name = "disp_engine1_sel",









		.parent_names = (const char *[]){"videopll1", "dsi_pll", "ldb_pll_div7", },









		.num_parents = 4,









		.parent_names = imx95_disp_engine_parents,









		.num_parents = ARRAY_SIZE(imx95_disp_engine_parents),









		.reg = 0,









		.bit_idx = 2,









		.bit_width = 2,








@@ -242,9 +247,9 @@ static const struct imx95_blk_ctl_clk_dev_data dispmix_csr_clk_dev_data[] = {







	}









};



















static const struct imx95_blk_ctl_dev_data dispmix_csr_dev_data = {









	.num_clks = ARRAY_SIZE(dispmix_csr_clk_dev_data),









	.clk_dev_data = dispmix_csr_clk_dev_data,









static const struct imx95_blk_ctl_dev_data imx95_dispmix_csr_dev_data = {









	.num_clks = ARRAY_SIZE(imx95_dispmix_csr_clk_dev_data),









	.clk_dev_data = imx95_dispmix_csr_clk_dev_data,









	.clk_reg_offset = 0,









};


















@@ -296,6 +301,51 @@ static const struct imx95_blk_ctl_dev_data hsio_blk_ctl_dev_data = {







	.clk_reg_offset = 0,









};



















static const struct imx95_blk_ctl_clk_dev_data imx94_lvds_clk_dev_data[] = {









	[IMX94_CLK_DISPMIX_LVDS_CLK_GATE] = {









		.name = "lvds_clk_gate",









		.parent_names = (const char *[]){ "ldbpll", },









		.num_parents = 1,









		.reg = 0,









		.bit_idx = 1,









		.bit_width = 1,









		.type = CLK_GATE,









		.flags = CLK_SET_RATE_PARENT,









		.flags2 = CLK_GATE_SET_TO_DISABLE,









	},









};



















static const struct imx95_blk_ctl_dev_data imx94_lvds_csr_dev_data = {









	.num_clks = ARRAY_SIZE(imx94_lvds_clk_dev_data),









	.clk_dev_data = imx94_lvds_clk_dev_data,









	.clk_reg_offset = 0,









	.rpm_enabled = true,









};



















static const char * const imx94_disp_engine_parents[] = {









	"disppix", "ldb_pll_div7"









};



















static const struct imx95_blk_ctl_clk_dev_data imx94_dispmix_csr_clk_dev_data[] = {









	[IMX94_CLK_DISPMIX_CLK_SEL] = {









		.name = "disp_clk_sel",









		.parent_names = imx94_disp_engine_parents,









		.num_parents = ARRAY_SIZE(imx94_disp_engine_parents),









		.reg = 0,









		.bit_idx = 1,









		.bit_width = 1,









		.type = CLK_MUX,









		.flags = CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT,









	},









};



















static const struct imx95_blk_ctl_dev_data imx94_dispmix_csr_dev_data = {









	.num_clks = ARRAY_SIZE(imx94_dispmix_csr_clk_dev_data),









	.clk_dev_data = imx94_dispmix_csr_clk_dev_data,









	.clk_reg_offset = 0,









	.rpm_enabled = true,









};



















static int imx95_bc_probe(struct platform_device *pdev)









{









	struct device *dev = &pdev->dev;








@@ -338,8 +388,10 @@ static int imx95_bc_probe(struct platform_device *pdev)







	if (!clk_hw_data)









		return -ENOMEM;



















	if (bc_data->rpm_enabled)









		pm_runtime_enable(&pdev->dev);









	if (bc_data->rpm_enabled) {









		devm_pm_runtime_enable(&pdev->dev);









		pm_runtime_resume_and_get(&pdev->dev);









	}



















	clk_hw_data->num = bc_data->num_clks;









	hws = clk_hw_data->hws;








@@ -379,8 +431,10 @@ static int imx95_bc_probe(struct platform_device *pdev)







		goto cleanup;









	}



















	if (pm_runtime_enabled(bc->dev))









	if (pm_runtime_enabled(bc->dev)) {









		pm_runtime_put_sync(&pdev->dev);









		clk_disable_unprepare(bc->clk_apb);









	}



















	return 0;


















@@ -391,9 +445,6 @@ static int imx95_bc_probe(struct platform_device *pdev)







		clk_hw_unregister(hws[i]);









	}



















	if (bc_data->rpm_enabled)









		pm_runtime_disable(&pdev->dev);



















	return ret;









}


















@@ -462,10 +513,12 @@ static const struct dev_pm_ops imx95_bc_pm_ops = {







};



















static const struct of_device_id imx95_bc_of_match[] = {









	{ .compatible = "nxp,imx94-display-csr", .data = &imx94_dispmix_csr_dev_data },









	{ .compatible = "nxp,imx94-lvds-csr", .data = &imx94_lvds_csr_dev_data },









	{ .compatible = "nxp,imx95-camera-csr", .data = &camblk_dev_data },









	{ .compatible = "nxp,imx95-display-master-csr", },









	{ .compatible = "nxp,imx95-lvds-csr", .data = &lvds_csr_dev_data },









	{ .compatible = "nxp,imx95-display-csr", .data = &dispmix_csr_dev_data },









	{ .compatible = "nxp,imx95-display-csr", .data = &imx95_dispmix_csr_dev_data },









	{ .compatible = "nxp,imx95-lvds-csr", .data = &imx95_lvds_csr_dev_data },









	{ .compatible = "nxp,imx95-hsio-blk-ctl", .data = &hsio_blk_ctl_dev_data },









	{ .compatible = "nxp,imx95-vpu-csr", .data = &vpublk_dev_data },









	{ .compatible = "nxp,imx95-netcmix-blk-ctrl", .data = &netcmix_dev_data},
































include/dt-bindings/clock/nxp,imx94-clock.h
0 → 100644



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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */









/*









 * Copyright 2025 NXP









 */



















#ifndef __DT_BINDINGS_CLOCK_IMX94_H









#define __DT_BINDINGS_CLOCK_IMX94_H



















#define IMX94_CLK_DISPMIX_CLK_SEL	0



















#define IMX94_CLK_DISPMIX_LVDS_CLK_GATE	0



















#endif /* __DT_BINDINGS_CLOCK_IMX94_H */