Commit f46fa84b authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Andi Shyti
Browse files

drm/i915: Use REG_BIT() & co. for ring fault registers 



Update the ring fault registers to use the modern REG_BIT()
stuff.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: default avatarAndi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20250211231941.22769-4-ville.syrjala@linux.intel.com
parent ecba96d2

drivers/gpu/drm/i915/gt/intel_gt.c

+10 −10
Original line number Diff line number Diff line
@@ -310,13 +310,13 @@ static void gen6_check_faults(struct intel_gt *gt) 
			gt_dbg(gt, "Unexpected fault\n"

			       "\tAddr: 0x%08lx\n"

			       "\tAddress space: %s\n"

			       "\tSource ID: %ld\n"

			       "\tType: %ld\n",

			       "\tSource ID: %d\n"

			       "\tType: %d\n",

			       fault & PAGE_MASK,

			       fault & RING_FAULT_GTTSEL_MASK ?

			       "GGTT" : "PPGTT",

			       RING_FAULT_SRCID(fault),

			       RING_FAULT_FAULT_TYPE(fault));

			       REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault),

			       REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault));

		}

	}

}
@@ -351,9 +351,9 @@ static void xehp_check_faults(struct intel_gt *gt) 
		       "\tType: %d\n",

		       upper_32_bits(fault_addr), lower_32_bits(fault_addr),

		       fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",

		       GEN8_RING_FAULT_ENGINE_ID(fault),

		       RING_FAULT_SRCID(fault),

		       RING_FAULT_FAULT_TYPE(fault));

		       REG_FIELD_GET(RING_FAULT_ENGINE_ID_MASK, fault),

		       REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault),

		       REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault));

	}

}
@@ -392,9 +392,9 @@ static void gen8_check_faults(struct intel_gt *gt) 
		       "\tType: %d\n",

		       upper_32_bits(fault_addr), lower_32_bits(fault_addr),

		       fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",

		       GEN8_RING_FAULT_ENGINE_ID(fault),

		       RING_FAULT_SRCID(fault),

		       RING_FAULT_FAULT_TYPE(fault));

		       REG_FIELD_GET(RING_FAULT_ENGINE_ID_MASK, fault),

		       REG_FIELD_GET(RING_FAULT_SRCID_MASK, fault),

		       REG_FIELD_GET(RING_FAULT_FAULT_TYPE_MASK, fault));

	}

}

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+7 −7
Original line number Diff line number Diff line
@@ -326,11 +326,11 @@ 
							    _RING_FAULT_REG_VCS, \

							    _RING_FAULT_REG_VECS, \

							    _RING_FAULT_REG_BCS))

#define   GEN8_RING_FAULT_ENGINE_ID(x)		(((x) >> 12) & 0x1f)

#define   RING_FAULT_GTTSEL_MASK		(1 << 11)

#define   RING_FAULT_SRCID(x)			(((x) >> 3) & 0xff)

#define   RING_FAULT_FAULT_TYPE(x)		(((x) >> 1) & 0x3)

#define   RING_FAULT_VALID			(1 << 0)

#define   RING_FAULT_ENGINE_ID_MASK		REG_GENMASK(16, 12)

#define   RING_FAULT_GTTSEL_MASK		REG_BIT(11)

#define   RING_FAULT_SRCID_MASK			REG_GENMASK(10, 3)

#define   RING_FAULT_FAULT_TYPE_MASK		REG_GENMASK(2, 1)

#define   RING_FAULT_VALID			REG_BIT(0)



#define ERROR_GEN6				_MMIO(0x40a0)
@@ -390,8 +390,8 @@ 


#define GEN8_FAULT_TLB_DATA0			_MMIO(0x4b10)

#define GEN8_FAULT_TLB_DATA1			_MMIO(0x4b14)

#define   FAULT_GTT_SEL				(1 << 4)

#define   FAULT_VA_HIGH_BITS			(0xf << 0)

#define   FAULT_GTT_SEL				REG_BIT(4)

#define   FAULT_VA_HIGH_BITS			REG_GENMASK(3, 0)



#define GEN11_GACB_PERF_CTRL			_MMIO(0x4b80)

#define   GEN11_HASH_CTRL_MASK			(0x3 << 12 | 0xf << 0)