Commit f4c16a7c authored by Abel Vesa's avatar Abel Vesa Committed by Bjorn Andersson
Browse files

clk: qcom: gcc-x1e80100: Fix USB 0 and 1 PHY GDSC pwrsts flags 



Allowing these GDSCs to collapse makes the QMP combo PHYs lose their
configuration on machine suspend. Currently, the QMP combo PHY driver
doesn't reinitialise the HW on resume. Under such conditions, the USB
SuperSpeed support is broken. To avoid this, mark the pwrsts flags with
RET_ON. This is in line with USB 2 PHY GDSC config.

Fixes: 161b7c40 ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20240801-x1e80100-clk-gcc-fix-usb-phy-gdscs-pwrsts-v1-1-8df016768a0f@linaro.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent f4973130

drivers/clk/qcom/gcc-x1e80100.c

+2 −2
Original line number Diff line number Diff line
@@ -6203,7 +6203,7 @@ static struct gdsc gcc_usb_0_phy_gdsc = { 
	.pd = {

		.name = "gcc_usb_0_phy_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

	.pwrsts = PWRSTS_RET_ON,

	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,

};
@@ -6215,7 +6215,7 @@ static struct gdsc gcc_usb_1_phy_gdsc = { 
	.pd = {

		.name = "gcc_usb_1_phy_gdsc",

	},

	.pwrsts = PWRSTS_OFF_ON,

	.pwrsts = PWRSTS_RET_ON,

	.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,

};