Commit f4c33ae8 authored by Daniele Ceraolo Spurio's avatar Daniele Ceraolo Spurio Committed by Rodrigo Vivi
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drm/xe: GSC forcewake support 



The ID for the GSC forcewake domain already exists, but we're missing
the register definitions and the domain intialization, so add that in.

v2: move reg definition to be in address order (Matt)

Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230817201831.1583172-6-daniele.ceraolospurio@intel.com


Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent aef61349

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+2 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ 
#define   GMD_ID_RELEASE_MASK			REG_GENMASK(21, 14)

#define   GMD_ID_REVID				REG_GENMASK(5, 0)



#define FORCEWAKE_ACK_GSC			XE_REG(0xdf8)

#define FORCEWAKE_ACK_GT_MTL			XE_REG(0xdfc)



/* L3 Cache Control */
@@ -256,6 +257,7 @@ 
#define FORCEWAKE_RENDER			XE_REG(0xa278)

#define FORCEWAKE_MEDIA_VDBOX(n)		XE_REG(0xa540 + (n) * 4)

#define FORCEWAKE_MEDIA_VEBOX(n)		XE_REG(0xa560 + (n) * 4)

#define FORCEWAKE_GSC				XE_REG(0xa618)



#define XEHPC_LNCFMISCCFGREG0			XE_REG_MCR(0xb01c, XE_REG_OPTION_MASKED)

#define   XEHPC_OVRLSCCC			REG_BIT(0)

drivers/gpu/drm/xe/xe_force_wake.c

+7 −0
Original line number Diff line number Diff line
@@ -97,6 +97,13 @@ void xe_force_wake_init_engines(struct xe_gt *gt, struct xe_force_wake *fw) 
			    FORCEWAKE_ACK_MEDIA_VEBOX(j),

			    BIT(0), BIT(16));

	}



	if (gt->info.engine_mask & BIT(XE_HW_ENGINE_GSCCS0))

		domain_init(&fw->domains[XE_FW_DOMAIN_ID_GSC],

			    XE_FW_DOMAIN_ID_GSC,

			    FORCEWAKE_GSC,

			    FORCEWAKE_ACK_GSC,

			    BIT(0), BIT(16));

}



static void domain_wake(struct xe_gt *gt, struct xe_force_wake_domain *domain)