Commit f4cc33e7 authored by Yu Chien Peter Lin's avatar Yu Chien Peter Lin Committed by Thomas Gleixner
Browse files

irqchip/riscv-intc: Introduce Andes hart-level interrupt controller 



Add support for the Andes hart-level interrupt controller. This
controller provides interrupt mask/unmask functions to access the
custom register (SLIE) where the non-standard S-mode local interrupt
enable bits are located. The base of custom interrupt number is set
to 256.

To share the riscv_intc_domain_map() with the generic RISC-V INTC and
ACPI, add a chip parameter to riscv_intc_init_common(), so it can be
passed to the irq_domain_set_info() as a private data.

Andes hart-level interrupt controller requires the "andestech,cpu-intc"
compatible string to be present in interrupt-controller of cpu node to
enable the use of custom local interrupt source.
e.g.,

  cpu0: cpu@0 {
      compatible = "andestech,ax45mp", "riscv";
      ...
      cpu0-intc: interrupt-controller {
          #interrupt-cells = <0x01>;
          compatible = "andestech,cpu-intc", "riscv,cpu-intc";
          interrupt-controller;
      };
  };

Signed-off-by: default avatarYu Chien Peter Lin <peterlin@andestech.com>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Reviewed-by: default avatarRandolph <randolph@andestech.com>
Reviewed-by: default avatarAnup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/r/20240222083946.3977135-4-peterlin@andestech.com
parent 96303bcb

drivers/irqchip/irq-riscv-intc.c

+51 −7
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include <linux/module.h>

#include <linux/of.h>

#include <linux/smp.h>

#include <linux/soc/andes/irq.h>



static struct irq_domain *intc_domain;

static unsigned int riscv_intc_nr_irqs __ro_after_init = BITS_PER_LONG;
@@ -48,6 +49,31 @@ static void riscv_intc_irq_unmask(struct irq_data *d) 
	csr_set(CSR_IE, BIT(d->hwirq));

}



static void andes_intc_irq_mask(struct irq_data *d)

{

	/*

	 * Andes specific S-mode local interrupt causes (hwirq)

	 * are defined as (256 + n) and controlled by n-th bit

	 * of SLIE.

	 */

	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);



	if (d->hwirq < ANDES_SLI_CAUSE_BASE)

		csr_clear(CSR_IE, mask);

	else

		csr_clear(ANDES_CSR_SLIE, mask);

}



static void andes_intc_irq_unmask(struct irq_data *d)

{

	unsigned int mask = BIT(d->hwirq % BITS_PER_LONG);



	if (d->hwirq < ANDES_SLI_CAUSE_BASE)

		csr_set(CSR_IE, mask);

	else

		csr_set(ANDES_CSR_SLIE, mask);

}



static void riscv_intc_irq_eoi(struct irq_data *d)

{

	/*
@@ -71,12 +97,21 @@ static struct irq_chip riscv_intc_chip = { 
	.irq_eoi = riscv_intc_irq_eoi,

};



static struct irq_chip andes_intc_chip = {

	.name		= "RISC-V INTC",

	.irq_mask	= andes_intc_irq_mask,

	.irq_unmask	= andes_intc_irq_unmask,

	.irq_eoi	= riscv_intc_irq_eoi,

};



static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,

				 irq_hw_number_t hwirq)

{

	struct irq_chip *chip = d->host_data;



	irq_set_percpu_devid(irq);

	irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,

			    handle_percpu_devid_irq, NULL, NULL);

	irq_domain_set_info(d, irq, hwirq, chip, NULL, handle_percpu_devid_irq,

			    NULL, NULL);



	return 0;

}
@@ -122,11 +157,12 @@ static struct fwnode_handle *riscv_intc_hwnode(void) 
	return intc_domain->fwnode;

}



static int __init riscv_intc_init_common(struct fwnode_handle *fn)

static int __init riscv_intc_init_common(struct fwnode_handle *fn,

					 struct irq_chip *chip)

{

	int rc;



	intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, NULL);

	intc_domain = irq_domain_create_tree(fn, &riscv_intc_domain_ops, chip);

	if (!intc_domain) {

		pr_err("unable to add IRQ domain\n");

		return -ENXIO;
@@ -152,8 +188,9 @@ static int __init riscv_intc_init_common(struct fwnode_handle *fn) 
static int __init riscv_intc_init(struct device_node *node,

				  struct device_node *parent)

{

	int rc;

	struct irq_chip *chip = &riscv_intc_chip;

	unsigned long hartid;

	int rc;



	rc = riscv_of_parent_hartid(node, &hartid);

	if (rc < 0) {
@@ -178,10 +215,17 @@ static int __init riscv_intc_init(struct device_node *node, 
		return 0;

	}



	return riscv_intc_init_common(of_node_to_fwnode(node));

	if (of_device_is_compatible(node, "andestech,cpu-intc")) {

		riscv_intc_custom_base = ANDES_SLI_CAUSE_BASE;

		riscv_intc_custom_nr_irqs = ANDES_RV_IRQ_LAST;

		chip = &andes_intc_chip;

	}



	return riscv_intc_init_common(of_node_to_fwnode(node), chip);

}



IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);

IRQCHIP_DECLARE(andes, "andestech,cpu-intc", riscv_intc_init);



#ifdef CONFIG_ACPI
@@ -208,7 +252,7 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, 
		return -ENOMEM;

	}



	return riscv_intc_init_common(fn);

	return riscv_intc_init_common(fn, &riscv_intc_chip);

}



IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL,

include/linux/soc/andes/irq.h

0 → 100644
+18 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (C) 2023 Andes Technology Corporation

 */

#ifndef __ANDES_IRQ_H

#define __ANDES_IRQ_H



/* Andes PMU irq number */

#define ANDES_RV_IRQ_PMOVI		18

#define ANDES_RV_IRQ_LAST		ANDES_RV_IRQ_PMOVI

#define ANDES_SLI_CAUSE_BASE		256



/* Andes PMU related registers */

#define ANDES_CSR_SLIE			0x9c4

#define ANDES_CSR_SLIP			0x9c5

#define ANDES_CSR_SCOUNTEROF		0x9d4



#endif /* __ANDES_IRQ_H */