Commit f4febfdb authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'timers-v6.7-rc1' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core 

Pull timer driver updates from Daniel Lezcano:

  - Fix DT bindings typos, readability and wrong information about
    underflow and overflow interrupts for the RZ/G2L MTU3a driver (Biju
    Das)

  - Fix a memory leak in the error path when probing the i.MX GPT timer
    (Jacky Bai)

  - Don't use clk_get_rate() in atomic context as the function might
    sleep. Store the clock and use notifiers to receive a clocke rate
    change notification (Ivaylo Dimitrov)

  - Remove superfluous error message when platform_get_irq() fails
    because the underlying function already prints one (Yang Li)

  - Add wakeup capability flag for the risc-V ACPI timer (Sunil V L)

  - Fix initialization of the TCB timers which are in cascade as the
    second timer is reset after the first wraps up leading to
    inconsistent scheduler behavior (Ronald Wahl)

  - Add DT bindings and driver for Cirrus Logic EP93xx (Nikita Shubin)
parents 8ceea12d c28ca80b

Documentation/devicetree/bindings/timer/cirrus,ep9301-timer.yaml

0 → 100644
+49 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/timer/cirrus,ep9301-timer.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Cirrus Logic EP93xx timer



maintainers:

  - Alexander Sverdlin <alexander.sverdlin@gmail.com>

  - Nikita Shubin <nikita.shubin@maquefel.me>



properties:

  compatible:

    oneOf:

      - const: cirrus,ep9301-timer

      - items:

          - enum:

              - cirrus,ep9302-timer

              - cirrus,ep9307-timer

              - cirrus,ep9312-timer

              - cirrus,ep9315-timer

          - const: cirrus,ep9301-timer



  reg:

    maxItems: 1



  interrupts:

    maxItems: 1



  resets:

    maxItems: 1



required:

  - compatible

  - reg

  - interrupts



additionalProperties: false



examples:

  - |

    timer@80810000 {

      compatible = "cirrus,ep9301-timer";

      reg = <0x80810000 0x100>;

      interrupt-parent = <&vic1>;

      interrupts = <19>;

    };

...

Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml

+34 −33
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ maintainers: 
description: |

  This hardware block consists of eight 16-bit timer channels and one

  32-bit timer channel. It supports the following specifications:

    - Pulse input/output: 28 lines max.

    - Pulse input/output: 28 lines max

    - Pulse input 3 lines

    - Count clock 11 clocks for each channel (14 clocks for MTU0, 12 clocks

      for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination
@@ -23,11 +23,11 @@ description: | 
        - Input capture function (noise filter setting available)

        - Counter-clearing operation

        - Simultaneous writing to multiple timer counters (TCNT)

          (excluding MTU8).

          (excluding MTU8)

        - Simultaneous clearing on compare match or input capture

          (excluding MTU8).

          (excluding MTU8)

        - Simultaneous input and output to registers in synchronization with

          counter operations           (excluding MTU8).

          counter operations (excluding MTU8)

        - Up to 12-phase PWM output in combination with synchronous operation

          (excluding MTU8)

    - [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
@@ -40,26 +40,26 @@ description: | 
    - [MTU3, MTU4, MTU6, and MTU7]

        - Through interlocked operation of MTU3/4 and MTU6/7, the positive and

          negative signals in six phases (12 phases in total) can be output in

          complementary PWM and reset-synchronized PWM operation.

          complementary PWM and reset-synchronized PWM operation

        - In complementary PWM mode, values can be transferred from buffer

          registers to temporary registers at crests and troughs of the timer-

          counter values or when the buffer registers (TGRD registers in MTU4

          and MTU7) are written to.

        - Double-buffering selectable in complementary PWM mode.

          and MTU7) are written to

        - Double-buffering selectable in complementary PWM mode

    - [MTU3 and MTU4]

        - Through interlocking with MTU0, a mode for driving AC synchronous

          motors (brushless DC motors) by using complementary PWM output and

          reset-synchronized PWM output is settable and allows the selection

          of two types of waveform output (chopping or level).

          of two types of waveform output (chopping or level)

    - [MTU5]

        - Capable of operation as a dead-time compensation counter.

        - Capable of operation as a dead-time compensation counter

    - [MTU0/MTU5, MTU1, MTU2, and MTU8]

        - 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and

          through interlocked operation with MTU0/MTU5 and MTU8.

          through interlocked operation with MTU0/MTU5 and MTU8

    - Interrupt-skipping function

        - In complementary PWM mode, interrupts on crests and troughs of counter

          values and triggers to start conversion by the A/D converter can be

          skipped.

          skipped

    - Interrupt sources: 43 sources.

    - Buffer operation:

        - Automatic transfer of register data (transfer from the buffer
@@ -68,9 +68,9 @@ description: | 
        - A/D converter start triggers can be generated

        - A/D converter start request delaying function enables A/D converter

          to be started with any desired timing and to be synchronized with

          PWM output.

          PWM output

    - Low power consumption function

        - The MTU3a can be placed in the module-stop state.

        - The MTU3a can be placed in the module-stop state



    There are two phase counting modes. 16-bit phase counting mode in which

    MTU1 and MTU2 operate independently, and cascade connection 32-bit phase
@@ -109,6 +109,7 @@ properties: 
  compatible:

    items:

      - enum:

          - renesas,r9a07g043-mtu3  # RZ/{G2UL,Five}

          - renesas,r9a07g044-mtu3  # RZ/G2{L,LC}

          - renesas,r9a07g054-mtu3  # RZ/V2L

      - const: renesas,rz-mtu3
@@ -169,27 +170,27 @@ properties: 
      - const: tgib0

      - const: tgic0

      - const: tgid0

      - const: tgiv0

      - const: tciv0

      - const: tgie0

      - const: tgif0

      - const: tgia1

      - const: tgib1

      - const: tgiv1

      - const: tgiu1

      - const: tciv1

      - const: tciu1

      - const: tgia2

      - const: tgib2

      - const: tgiv2

      - const: tgiu2

      - const: tciv2

      - const: tciu2

      - const: tgia3

      - const: tgib3

      - const: tgic3

      - const: tgid3

      - const: tgiv3

      - const: tciv3

      - const: tgia4

      - const: tgib4

      - const: tgic4

      - const: tgid4

      - const: tgiv4

      - const: tciv4

      - const: tgiu5

      - const: tgiv5

      - const: tgiw5
@@ -197,18 +198,18 @@ properties: 
      - const: tgib6

      - const: tgic6

      - const: tgid6

      - const: tgiv6

      - const: tciv6

      - const: tgia7

      - const: tgib7

      - const: tgic7

      - const: tgid7

      - const: tgiv7

      - const: tciv7

      - const: tgia8

      - const: tgib8

      - const: tgic8

      - const: tgid8

      - const: tgiv8

      - const: tgiu8

      - const: tciv8

      - const: tciu8



  clocks:

    maxItems: 1
@@ -285,16 +286,16 @@ examples: 
                   <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,

                   <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;

      interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tgiv0", "tgie0",

      interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tciv0", "tgie0",

                        "tgif0",

                        "tgia1", "tgib1", "tgiv1", "tgiu1",

                        "tgia2", "tgib2", "tgiv2", "tgiu2",

                        "tgia3", "tgib3", "tgic3", "tgid3", "tgiv3",

                        "tgia4", "tgib4", "tgic4", "tgid4", "tgiv4",

                        "tgia1", "tgib1", "tciv1", "tciu1",

                        "tgia2", "tgib2", "tciv2", "tciu2",

                        "tgia3", "tgib3", "tgic3", "tgid3", "tciv3",

                        "tgia4", "tgib4", "tgic4", "tgid4", "tciv4",

                        "tgiu5", "tgiv5", "tgiw5",

                        "tgia6", "tgib6", "tgic6", "tgid6", "tgiv6",

                        "tgia7", "tgib7", "tgic7", "tgid7", "tgiv7",

                        "tgia8", "tgib8", "tgic8", "tgid8", "tgiv8", "tgiu8";

                        "tgia6", "tgib6", "tgic6", "tgid6", "tciv6",

                        "tgia7", "tgib7", "tgic7", "tgid7", "tciv7",

                        "tgia8", "tgib8", "tgic8", "tgid8", "tciv8", "tciu8";

      clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;

      power-domains = <&cpg>;

      resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;

drivers/clocksource/Kconfig

+11 −0
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@@ -732,4 +732,15 @@ config GOLDFISH_TIMER 
	help

	  Support for the timer/counter of goldfish-rtc



config EP93XX_TIMER

	bool "Cirrus Logic ep93xx timer driver" if COMPILE_TEST

	depends on ARCH_EP93XX

	depends on GENERIC_CLOCKEVENTS

	depends on HAS_IOMEM

	select CLKSRC_MMIO

	select TIMER_OF

	help

	  Enables support for the Cirrus Logic timer block

	  EP93XX.



endmenu

drivers/clocksource/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -89,3 +89,4 @@ obj-$(CONFIG_MSC313E_TIMER) += timer-msc313e.o 
obj-$(CONFIG_GOLDFISH_TIMER)		+= timer-goldfish.o

obj-$(CONFIG_GXP_TIMER)			+= timer-gxp.o

obj-$(CONFIG_CLKSRC_LOONGSON1_PWM)	+= timer-loongson1-pwm.o

obj-$(CONFIG_EP93XX_TIMER)		+= timer-ep93xx.o

drivers/clocksource/timer-atmel-tcb.c

+1 −0
Original line number Diff line number Diff line
@@ -315,6 +315,7 @@ static void __init tcb_setup_dual_chan(struct atmel_tc *tc, int mck_divisor_idx) 
	writel(mck_divisor_idx			/* likely divide-by-8 */

			| ATMEL_TC_WAVE

			| ATMEL_TC_WAVESEL_UP		/* free-run */

			| ATMEL_TC_ASWTRG_SET		/* TIOA0 rises at software trigger */

			| ATMEL_TC_ACPA_SET		/* TIOA0 rises at 0 */

			| ATMEL_TC_ACPC_CLEAR,		/* (duty cycle 50%) */

			tcaddr + ATMEL_TC_REG(0, CMR));