Commit f521678d authored by Svyatoslav Ryhel's avatar Svyatoslav Ryhel Committed by Thierry Reding
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clk: tegra20: Reparent dsi clock to pll_d_out0 



Reparent DSI clock to PLLD_OUT0 instead of directly descend from PLLD.

Signed-off-by: default avatarSvyatoslav Ryhel <clamor95@gmail.com>
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Reviewed-by: default avatarMikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 2ea99dad

drivers/clk/tegra/clk-tegra20.c

+3 −3
Original line number Diff line number Diff line
@@ -802,9 +802,9 @@ static void __init tegra20_periph_clk_init(void) 
	clks[TEGRA20_CLK_MC] = clk;



	/* dsi */

	clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,

				    48, periph_clk_enb_refcnt);

	clk_register_clkdev(clk, NULL, "dsi");

	clk = tegra_clk_register_periph_gate("dsi", "pll_d_out0", 0,

					     clk_base, 0, TEGRA20_CLK_DSI,

					     periph_clk_enb_refcnt);

	clks[TEGRA20_CLK_DSI] = clk;



	/* pex */