Merge tag 'drm-xe-next-2025-10-28' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-next (f53128e3) · Commits · git / linux-net

drivers/gpu/drm/xe/display/xe_panic.c

+36 −14

Original line number	Diff line number	Diff line
		@@ -8,20 +8,23 @@
		#include "intel_fb.h"
		#include "intel_panic.h"
		#include "xe_bo.h"
		#include "xe_res_cursor.h"

		struct intel_panic {
		struct page **pages;
		struct xe_res_cursor res;
		struct iosys_map vmap;

		int page;
		void *vaddr;
		};

		static void xe_panic_kunmap(struct intel_panic *panic)
		{
		if (panic->vaddr) {
		drm_clflush_virt_range(panic->vaddr, PAGE_SIZE);
		kunmap_local(panic->vaddr);
		panic->vaddr = NULL;
		if (!panic->vmap.is_iomem && iosys_map_is_set(&panic->vmap)) {
		drm_clflush_virt_range(panic->vmap.vaddr, PAGE_SIZE);
		kunmap_local(panic->vmap.vaddr);
		}
		iosys_map_clear(&panic->vmap);
		panic->page = -1;
		}

		/*
		@@ -46,15 +49,29 @@ static void xe_panic_page_set_pixel(struct drm_scanout_buffer *sb, unsigned int
		new_page = offset >> PAGE_SHIFT;
		offset = offset % PAGE_SIZE;
		if (new_page != panic->page) {
		if (xe_bo_is_vram(bo)) {
		/* Display is always mapped on root tile */
		struct xe_vram_region *vram = xe_bo_device(bo)->mem.vram;

		if (panic->page < 0 \|\| new_page < panic->page) {
		xe_res_first(bo->ttm.resource, new_page * PAGE_SIZE,
		bo->ttm.base.size - new_page * PAGE_SIZE, &panic->res);
		} else {
		xe_res_next(&panic->res, PAGE_SIZE * (new_page - panic->page));
		}
		iosys_map_set_vaddr_iomem(&panic->vmap,
		vram->mapping + panic->res.start);
		} else {
		xe_panic_kunmap(panic);
		panic->page = new_page;
		panic->vaddr = ttm_bo_kmap_try_from_panic(&bo->ttm,
		panic->page);
		iosys_map_set_vaddr(&panic->vmap,
		ttm_bo_kmap_try_from_panic(&bo->ttm,
		new_page));
		}
		if (panic->vaddr) {
		u32 *pix = panic->vaddr + offset;
		*pix = color;
		panic->page = new_page;
		}

		if (iosys_map_is_set(&panic->vmap))
		iosys_map_wr(&panic->vmap, offset, u32, color);
		}

		struct intel_panic *intel_panic_alloc(void)
		@@ -68,6 +85,12 @@ struct intel_panic *intel_panic_alloc(void)

		int intel_panic_setup(struct intel_panic panic, struct drm_scanout_buffer sb)
		{
		struct intel_framebuffer fb = (struct intel_framebuffer )sb->private;
		struct xe_bo *bo = gem_to_xe_bo(intel_fb_bo(&fb->base));

		if (xe_bo_is_vram(bo) && !xe_bo_is_visible_vram(bo))
		return -ENODEV;

		panic->page = -1;
		sb->set_pixel = xe_panic_page_set_pixel;
		return 0;
		@@ -76,5 +99,4 @@ int intel_panic_setup(struct intel_panic panic, struct drm_scanout_buffer sb)
		void intel_panic_finish(struct intel_panic *panic)
		{
		xe_panic_kunmap(panic);
		panic->page = -1;
		}

drivers/gpu/drm/xe/instructions/xe_gpu_commands.h

+6 −0

Original line number	Diff line number	Diff line
		@@ -31,6 +31,12 @@
		#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30)
		#define XE2_XY_FAST_COPY_BLT_MOCS_INDEX_MASK GENMASK(23, 20)

		#define MEM_COPY_CMD (2 << 29 \| 0x5a << 22 \| 0x8)
		#define MEM_COPY_PAGE_COPY_MODE REG_BIT(19)
		#define MEM_COPY_MATRIX_COPY REG_BIT(17)
		#define MEM_COPY_SRC_MOCS_INDEX_MASK GENMASK(31, 28)
		#define MEM_COPY_DST_MOCS_INDEX_MASK GENMASK(6, 3)

		#define PVC_MEM_SET_CMD (2 << 29 \| 0x5b << 22)
		#define PVC_MEM_SET_CMD_LEN_DW 7
		#define PVC_MEM_SET_MATRIX REG_BIT(17)

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+10 −0

Original line number	Diff line number	Diff line
		@@ -37,6 +37,12 @@
		#define GMD_ID XE_REG(0xd8c)
		#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
		#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
		/*
		* Spec defines these bits as "Reserved", but then make them assume some
		* meaning that depends on the ARCH. To avoid any confusion, call them
		* SUBIP_FLAG_MASK.
		*/
		#define GMD_ID_SUBIP_FLAG_MASK REG_GENMASK(13, 6)
		#define GMD_ID_REVID REG_GENMASK(5, 0)

		#define FORCEWAKE_ACK_GSC XE_REG(0xdf8)
		@@ -168,6 +174,7 @@

		#define XEHP_SLICE_COMMON_ECO_CHICKEN1 XE_REG_MCR(0x731c, XE_REG_OPTION_MASKED)
		#define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14)
		#define FAST_CLEAR_VALIGN_FIX REG_BIT(13)

		#define XE2LPM_CCCHKNREG1 XE_REG(0x82a8)

		@@ -544,6 +551,9 @@
		#define SARB_CHICKEN1 XE_REG_MCR(0xe90c)
		#define COMP_CKN_IN REG_GENMASK(30, 29)

		#define MAIN_GAMCTRL_MODE XE_REG(0xef00)
		#define MAIN_GAMCTRL_QUEUE_SELECT REG_BIT(0)

		#define RCU_MODE XE_REG(0x14800, XE_REG_OPTION_MASKED)
		#define RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)
		#define RCU_MODE_CCS_ENABLE REG_BIT(0)

drivers/gpu/drm/xe/tests/xe_pci_test.c

+11 −5

Original line number	Diff line number	Diff line
		@@ -44,21 +44,27 @@ static void check_media_ip(struct kunit *test)
		KUNIT_ASSERT_EQ(test, mask, 0);
		}

		static void check_platform_gt_count(struct kunit *test)
		static void check_platform_desc(struct kunit *test)
		{
		const struct pci_device_id *pci = test->param_value;
		const struct xe_device_desc *desc =
		(const struct xe_device_desc *)pci->driver_data;
		int max_gt = desc->max_gt_per_tile;

		KUNIT_ASSERT_GT(test, max_gt, 0);
		KUNIT_ASSERT_LE(test, max_gt, XE_MAX_GT_PER_TILE);
		KUNIT_EXPECT_GT(test, desc->dma_mask_size, 0);

		KUNIT_EXPECT_GT(test, (unsigned int)desc->max_gt_per_tile, 0);
		KUNIT_EXPECT_LE(test, (unsigned int)desc->max_gt_per_tile, XE_MAX_GT_PER_TILE);

		KUNIT_EXPECT_GT(test, desc->va_bits, 0);
		KUNIT_EXPECT_LE(test, desc->va_bits, 64);

		KUNIT_EXPECT_GT(test, desc->vm_max_level, 0);
		}

		static struct kunit_case xe_pci_tests[] = {
		KUNIT_CASE_PARAM(check_graphics_ip, xe_pci_graphics_ip_gen_param),
		KUNIT_CASE_PARAM(check_media_ip, xe_pci_media_ip_gen_param),
		KUNIT_CASE_PARAM(check_platform_gt_count, xe_pci_id_gen_param),
		KUNIT_CASE_PARAM(check_platform_desc, xe_pci_id_gen_param),
		{}
		};

drivers/gpu/drm/xe/xe_bo.c

+26 −3

Original line number	Diff line number	Diff line
		@@ -610,6 +610,23 @@ static bool xe_ttm_resource_visible(struct ttm_resource *mem)
		return vres->used_visible_size == mem->size;
		}

		/**
		* xe_bo_is_visible_vram - check if BO is placed entirely in visible VRAM.
		* @bo: The BO
		*
		* This function checks whether a given BO resides entirely in memory visible from the CPU
		*
		* Returns: true if the BO is entirely visible, false otherwise.
		*
		*/
		bool xe_bo_is_visible_vram(struct xe_bo *bo)
		{
		if (drm_WARN_ON(bo->ttm.base.dev, !xe_bo_is_vram(bo)))
		return false;

		return xe_ttm_resource_visible(bo->ttm.resource);
		}

		static int xe_ttm_io_mem_reserve(struct ttm_device *bdev,
		struct ttm_resource *mem)
		{
		@@ -1635,7 +1652,7 @@ static int xe_ttm_access_memory(struct ttm_buffer_object *ttm_bo,
		if (!mem_type_is_vram(ttm_bo->resource->mem_type))
		return -EIO;

		if (!xe_ttm_resource_visible(ttm_bo->resource) \|\| len >= SZ_16K) {
		if (!xe_bo_is_visible_vram(bo) \|\| len >= SZ_16K) {
		struct xe_migrate *migrate =
		mem_type_to_migrate(xe, ttm_bo->resource->mem_type);

		@@ -2105,7 +2122,7 @@ void xe_bo_free(struct xe_bo *bo)
		* if the function should allocate a new one.
		* @tile: The tile to select for migration of this bo, and the tile used for
		* GGTT binding if any. Only to be non-NULL for ttm_bo_type_kernel bos.
		* @resv: Pointer to a locked shared reservation object to use fo this bo,
		* @resv: Pointer to a locked shared reservation object to use for this bo,
		* or NULL for the xe_bo to use its own.
		* @bulk: The bulk move to use for LRU bumping, or NULL for external bos.
		* @size: The storage size to use for the bo.
		@@ -2259,6 +2276,12 @@ static int __xe_bo_fixed_placement(struct xe_device *xe,
		struct ttm_place *place = bo->placements;
		u32 vram_flag, vram_stolen_flags;

		/*
		* to allow fixed placement in GGTT of a VF, post-migration fixups would have to
		* include selecting a new fixed offset and shifting the page ranges for it
		*/
		xe_assert(xe, !IS_SRIOV_VF(xe) \|\| !(bo->flags & XE_BO_FLAG_GGTT));

		if (flags & (XE_BO_FLAG_USER \| XE_BO_FLAG_SYSTEM))
		return -EINVAL;

		@@ -2629,7 +2652,7 @@ struct xe_bo xe_bo_create_pin_map(struct xe_device xe, struct xe_tile *tile,
		* @size: The storage size to use for the bo.
		* @type: The TTM buffer object type.
		* @flags: XE_BO_FLAG_ flags.
		* @intr: Whether to execut any waits for backing store interruptible.
		* @intr: Whether to execute any waits for backing store interruptible.
		*
		* Create a pinned and mapped bo. The bo will be external and not associated
		* with a VM.