Commit f53d0f48 authored by Yiling Chen's avatar Yiling Chen Committed by Alex Deucher
Browse files

drm/amd/display: To apply the adjusted DP ref clock for DP devices 



[Why]
For some pixel clock margin sensitive external monitor,
we could not keep original DP ref clock for the ASICs
supported SSC DP ref clock.

[How]
From slicon design team's comment,
we have to apply the adjusted DP ref clock for
DP devices.
DP 128b (DP2) signals uses the DTBCLK not DP ref.

Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarYiling Chen <yi-ling.chen2@amd.com>
Signed-off-by: default avatarZaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: default avatarMark Broadworth <mark.broadworth@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent eec64449

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c

+5 −4
Original line number Diff line number Diff line
@@ -976,11 +976,12 @@ static bool dcn31_program_pix_clk( 
	struct bp_pixel_clock_parameters bp_pc_params = {0};

	enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24;



	// Apply ssed(spread spectrum) dpref clock for edp only.

	if (clock_source->ctx->dc->clk_mgr->dp_dto_source_clock_in_khz != 0

		&& pix_clk_params->signal_type == SIGNAL_TYPE_EDP

		&& encoding == DP_8b_10b_ENCODING)

	// Apply ssed(spread spectrum) dpref clock for edp and dp

	if (clock_source->ctx->dc->clk_mgr->dp_dto_source_clock_in_khz != 0 &&

		dc_is_dp_signal(pix_clk_params->signal_type) &&

		encoding == DP_8b_10b_ENCODING)

		dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dp_dto_source_clock_in_khz;



	// For these signal types Driver to program DP_DTO without calling VBIOS Command table

	if (dc_is_dp_signal(pix_clk_params->signal_type) || dc_is_virtual_signal(pix_clk_params->signal_type)) {

		if (e) {