Commit f53e8676 authored by Robin Getz's avatar Robin Getz Committed by Bryan Wu
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[Blackfin] arch: Add a note describing what is going on - no functional changes 



Signed-off-by: default avatarRobin Getz <robin.getz@analog.com>
Signed-off-by: default avatarBryan Wu <bryan.wu@analog.com>
parent 326e96b9

arch/blackfin/mach-common/cplbmgr.S

+13 −2
Original line number Diff line number Diff line
@@ -75,6 +75,15 @@ ENTRY(_cplb_mgr) 
	* from the configuration table.

	*/



	/* A multi-word instruction can cross a page boundary. This means the

	 * first part of the instruction can be in a valid page, but the

	 * second part is not, and hence generates the instruction miss.

	 * However, the fault address is for the start of the instruction,

	 * not the part that's in the bad page. Therefore, we have to check

	 * whether the fault address applies to a page that is already present

	 * in the table.

	 */



	P4.L = LO(ICPLB_FAULT_ADDR);

	P4.H = HI(ICPLB_FAULT_ADDR);
@@ -87,7 +96,7 @@ ENTRY(_cplb_mgr) 
	R4 = [P4];		/* Get faulting address*/

	R6 = 64;		/* Advance past the fault address, which*/

	R6 = R6 + R4;		/* we'll use if we find a match*/

	R3 = ((16 << 8) | 2);	/* Extract mask, bits 16 and 17.*/

	R3 = ((16 << 8) | 2);	/* Extract mask, two bits at posn 16 */



	R5 = 0;

.Lisearch:
@@ -125,7 +134,9 @@ ENTRY(_cplb_mgr) 
	P4.L = LO(IMEM_CONTROL);

	P4.H = HI(IMEM_CONTROL);



	/* disable cplbs */

	/* Turn off CPLBs while we work, necessary according to HRM before

	 * modifying CPLB descriptors

	 */

	R5 = [P4];		/* Control Register*/

	BITCLR(R5,ENICPLB_P);

	CLI R1;