Commit f540f692 authored by Shashank Sharma's avatar Shashank Sharma Committed by Alex Deucher
Browse files

drm/amdgpu: add kernel config for gfx-userqueue 



This patch:
- adds a kernel config option "CONFIG_DRM_AMDGPU_NAVI3X_USERQ"
- moves the usequeue initialization code for all IPs under
  this flag
- cover the core userqueue functions under this config
- adds stub function for userqueue ioctl.

so that the userqueue works only when the config is enabled.

V9:  Introduce this patch
V10: Call it CONFIG_DRM_AMDGPU_NAVI3X_USERQ instead of
     CONFIG_DRM_AMDGPU_USERQ_GFX (Christian)
V11: Add GFX in the config help description message.
V12: Add depends on BROKEN for this config, remove this when the rest of
the code is available.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian Koenig <christian.koenig@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarShashank Sharma <shashank.sharma@amd.com>
Signed-off-by: default avatarArvind Yadav <arvind.yadav@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9d3afcb7

drivers/gpu/drm/amd/amdgpu/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -96,6 +96,15 @@ config DRM_AMDGPU_WERROR 
	  Add -Werror to the build flags for amdgpu.ko.

	  Only enable this if you are warning code for amdgpu.ko.



config DRM_AMDGPU_NAVI3X_USERQ

	bool "Enable Navi 3x gfx usermode queues"

	depends on DRM_AMDGPU

	depends on BROKEN

	default n

	help

	  Choose this option to enable GFX usermode queue support for GFX/SDMA/Compute

          workload submission. This feature is experimental and supported on Navi 3X only.



source "drivers/gpu/drm/amd/acp/Kconfig"

source "drivers/gpu/drm/amd/display/Kconfig"

source "drivers/gpu/drm/amd/amdkfd/Kconfig"

drivers/gpu/drm/amd/amdgpu/Makefile

+3 −1
Original line number Diff line number Diff line
@@ -175,7 +175,9 @@ amdgpu-y += \ 
	amdgpu_mes.o \

	mes_v11_0.o \

	mes_v12_0.o \

	mes_v11_0_userqueue.o



# add GFX userqueue support

amdgpu-$(CONFIG_DRM_AMDGPU_NAVI3X_USERQ) += mes_v11_0_userqueue.o



# add UVD block

amdgpu-y += \

drivers/gpu/drm/amd/amdgpu/amdgpu_userqueue.c

+8 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ amdgpu_userqueue_cleanup(struct amdgpu_userq_mgr *uq_mgr, 
	kfree(queue);

}



#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ

static struct amdgpu_usermode_queue *

amdgpu_userqueue_find(struct amdgpu_userq_mgr *uq_mgr, int qid)

{
@@ -279,6 +280,13 @@ int amdgpu_userq_ioctl(struct drm_device *dev, void *data, 


	return r;

}

#else

int amdgpu_userq_ioctl(struct drm_device *dev, void *data,

		       struct drm_file *filp)

{

	return 0;

}

#endif



int amdgpu_userq_mgr_init(struct amdgpu_userq_mgr *userq_mgr, struct amdgpu_device *adev)

{

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+4 −0
Original line number Diff line number Diff line
@@ -1614,8 +1614,10 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 
		adev->gfx.mec.num_mec = 1;

		adev->gfx.mec.num_pipe_per_mec = 4;

		adev->gfx.mec.num_queue_per_pipe = 4;

#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ

		adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_v11_0_funcs;

		adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_v11_0_funcs;

#endif

		break;

	case IP_VERSION(11, 0, 1):

	case IP_VERSION(11, 0, 4):
@@ -1629,8 +1631,10 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block) 
		adev->gfx.mec.num_mec = 1;

		adev->gfx.mec.num_pipe_per_mec = 4;

		adev->gfx.mec.num_queue_per_pipe = 4;

#ifdef CONFIG_DRM_AMD_USERQ_GFX

		adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_v11_0_funcs;

		adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_v11_0_funcs;

#endif

		break;

	default:

		adev->gfx.me.num_me = 1;

drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

+2 −1
Original line number Diff line number Diff line
@@ -1377,8 +1377,9 @@ static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block) 
	else

		DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");



#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ

	adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_v11_0_funcs;



#endif

	r = amdgpu_sdma_sysfs_reset_mask_init(adev);

	if (r)

		return r;