Commit f552a7c7 authored by Balamanikandan Gunasundar's avatar Balamanikandan Gunasundar Committed by Miquel Raynal
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mtd: rawnand: atmel: set pmecc data setup time 



Setup the pmecc data setup time as 3 clock cycles for 133MHz as recommended
by the datasheet.

Fixes: f88fc122 ("mtd: nand: Cleanup/rework the atmel_nand driver")
Reported-by: default avatarZixun LI <admin@hifiphile.com>
Closes: https://lore.kernel.org/all/c015bb20-6a57-4f63-8102-34b3d83e0f5b@microchip.com


Suggested-by: default avatarAda Couprie Diaz <ada.coupriediaz@arm.com>
Signed-off-by: default avatarBalamanikandan Gunasundar <balamanikandan.gunasundar@microchip.com>
Signed-off-by: default avatarMiquel Raynal <miquel.raynal@bootlin.com>
parent 091d9e35

drivers/mtd/nand/raw/atmel/pmecc.c

+6 −0
Original line number Diff line number Diff line
@@ -143,6 +143,7 @@ struct atmel_pmecc_caps { 
	int nstrengths;

	int el_offset;

	bool correct_erased_chunks;

	bool clk_ctrl;

};



struct atmel_pmecc {
@@ -843,6 +844,10 @@ static struct atmel_pmecc *atmel_pmecc_create(struct platform_device *pdev, 
	if (IS_ERR(pmecc->regs.errloc))

		return ERR_CAST(pmecc->regs.errloc);



	/* pmecc data setup time */

	if (caps->clk_ctrl)

		writel(PMECC_CLK_133MHZ, pmecc->regs.base + ATMEL_PMECC_CLK);



	/* Disable all interrupts before registering the PMECC handler. */

	writel(0xffffffff, pmecc->regs.base + ATMEL_PMECC_IDR);

	atmel_pmecc_reset(pmecc);
@@ -896,6 +901,7 @@ static struct atmel_pmecc_caps at91sam9g45_caps = { 
	.strengths = atmel_pmecc_strengths,

	.nstrengths = 5,

	.el_offset = 0x8c,

	.clk_ctrl = true,

};



static struct atmel_pmecc_caps sama5d4_caps = {