Commit f557af08 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'riscv-for-linus-6.11-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V updates from Palmer Dabbelt:

 - Support for various new ISA extensions:
     * The Zve32[xf] and Zve64[xfd] sub-extensios of the vector
       extension
     * Zimop and Zcmop for may-be-operations
     * The Zca, Zcf, Zcd and Zcb sub-extensions of the C extension
     * Zawrs

 - riscv,cpu-intc is now dtschema

 - A handful of performance improvements and cleanups to text patching

 - Support for memory hot{,un}plug

 - The highest user-allocatable virtual address is now visible in
   hwprobe

* tag 'riscv-for-linus-6.11-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (58 commits)
  riscv: lib: relax assembly constraints in hweight
  riscv: set trap vector earlier
  KVM: riscv: selftests: Add Zawrs extension to get-reg-list test
  KVM: riscv: Support guest wrs.nto
  riscv: hwprobe: export Zawrs ISA extension
  riscv: Add Zawrs support for spinlocks
  dt-bindings: riscv: Add Zawrs ISA extension description
  riscv: Provide a definition for 'pause'
  riscv: hwprobe: export highest virtual userspace address
  riscv: Improve sbi_ecall() code generation by reordering arguments
  riscv: Add tracepoints for SBI calls and returns
  riscv: Optimize crc32 with Zbc extension
  riscv: Enable DAX VMEMMAP optimization
  riscv: mm: Add support for ZONE_DEVICE
  virtio-mem: Enable virtio-mem for RISC-V
  riscv: Enable memory hotplugging for RISC-V
  riscv: mm: Take memory hotplug read-lock during kernel page table dump
  riscv: mm: Add memory hotplugging support
  riscv: mm: Add pfn_to_kaddr() implementation
  riscv: mm: Refactor create_linear_mapping_range() for memory hot add
  ...
parents d2be38b9 93b63f68
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@@ -192,6 +192,53 @@ The following keys are defined:
       supported as defined in the RISC-V ISA manual starting from commit
       d8ab5c78c207 ("Zihintpause is ratified").

  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is
    supported, as defined by version 1.0 of the RISC-V Vector extension manual.

  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is
    supported, as defined by version 1.0 of the RISC-V Vector extension manual.

  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is
    supported, as defined by version 1.0 of the RISC-V Vector extension manual.

  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is
    supported, as defined by version 1.0 of the RISC-V Vector extension manual.

  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is
    supported, as defined by version 1.0 of the RISC-V Vector extension manual.

  * :c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension is
       supported as defined in the RISC-V ISA manual starting from commit
       58220614a5f ("Zimop is ratified/1.0").

  * :c:macro:`RISCV_HWPROBE_EXT_ZCA`: The Zca extension part of Zc* standard
       extensions for code size reduction, as ratified in commit 8be3419c1c0
       ("Zcf doesn't exist on RV64 as it contains no instructions") of
       riscv-code-size-reduction.

  * :c:macro:`RISCV_HWPROBE_EXT_ZCB`: The Zcb extension part of Zc* standard
       extensions for code size reduction, as ratified in commit 8be3419c1c0
       ("Zcf doesn't exist on RV64 as it contains no instructions") of
       riscv-code-size-reduction.

  * :c:macro:`RISCV_HWPROBE_EXT_ZCD`: The Zcd extension part of Zc* standard
       extensions for code size reduction, as ratified in commit 8be3419c1c0
       ("Zcf doesn't exist on RV64 as it contains no instructions") of
       riscv-code-size-reduction.

  * :c:macro:`RISCV_HWPROBE_EXT_ZCF`: The Zcf extension part of Zc* standard
       extensions for code size reduction, as ratified in commit 8be3419c1c0
       ("Zcf doesn't exist on RV64 as it contains no instructions") of
       riscv-code-size-reduction.

  * :c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extension is
       supported as defined in the RISC-V ISA manual starting from commit
       c732a4f39a4 ("Zcmop is ratified/1.0").

  * :c:macro:`RISCV_HWPROBE_EXT_ZAWRS`: The Zawrs extension is supported as
       ratified in commit 98918c844281 ("Merge pull request #1217 from
       riscv/zawrs") of riscv-isa-manual.

* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
  information about the selected set of processors.

@@ -214,3 +261,6 @@ The following keys are defined:

* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which
  represents the size of the Zicboz block in bytes.

* :c:macro:`RISCV_HWPROBE_KEY_HIGHEST_VIRT_ADDRESS`: An unsigned long which
  represent the highest userspace virtual address usable.
+0 −52
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RISC-V Hart-Level Interrupt Controller (HLIC)
---------------------------------------------

RISC-V cores include Control Status Registers (CSRs) which are local to each
CPU core (HART in RISC-V terminology) and can be read or written by software.
Some of these CSRs are used to control local interrupts connected to the core.
Every interrupt is ultimately routed through a hart's HLIC before it
interrupts that hart.

The RISC-V supervisor ISA manual specifies three interrupt sources that are
attached to every HLIC: software interrupts, the timer interrupt, and external
interrupts.  Software interrupts are used to send IPIs between cores.  The
timer interrupt comes from an architecturally mandated real-time timer that is
controlled via Supervisor Binary Interface (SBI) calls and CSR reads.  External
interrupts connect all other device interrupts to the HLIC, which are routed
via the platform-level interrupt controller (PLIC).

All RISC-V systems that conform to the supervisor ISA specification are
required to have a HLIC with these three interrupt sources present.  Since the
interrupt map is defined by the ISA it's not listed in the HLIC's device tree
entry, though external interrupt controllers (like the PLIC, for example) will
need to define how their interrupts map to the relevant HLICs.  This means
a PLIC interrupt property will typically list the HLICs for all present HARTs
in the system.

Required properties:
- compatible : "riscv,cpu-intc"
- #interrupt-cells : should be <1>.  The interrupt sources are defined by the
  RISC-V supervisor ISA manual, with only the following three interrupts being
  defined for supervisor mode:
    - Source 1 is the supervisor software interrupt, which can be sent by an SBI
      call and is reserved for use by software.
    - Source 5 is the supervisor timer interrupt, which can be configured by
      SBI calls and implements a one-shot timer.
    - Source 9 is the supervisor external interrupt, which chains to all other
      device interrupts.
- interrupt-controller : Identifies the node as an interrupt controller

Furthermore, this interrupt-controller MUST be embedded inside the cpu
definition of the hart whose CSRs control these local interrupts.

An example device tree entry for a HLIC is show below.

	cpu1: cpu@1 {
		compatible = "riscv";
		...
		cpu1-intc: interrupt-controller {
			#interrupt-cells = <1>;
			compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc";
			interrupt-controller;
		};
	};
+73 −0
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# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: RISC-V Hart-Level Interrupt Controller (HLIC)

description:
  RISC-V cores include Control Status Registers (CSRs) which are local to
  each CPU core (HART in RISC-V terminology) and can be read or written by
  software. Some of these CSRs are used to control local interrupts connected
  to the core. Every interrupt is ultimately routed through a hart's HLIC
  before it interrupts that hart.

  The RISC-V supervisor ISA manual specifies three interrupt sources that are
  attached to every HLIC namely software interrupts, the timer interrupt, and
  external interrupts. Software interrupts are used to send IPIs between
  cores.  The timer interrupt comes from an architecturally mandated real-
  time timer that is controlled via Supervisor Binary Interface (SBI) calls
  and CSR reads. External interrupts connect all other device interrupts to
  the HLIC, which are routed via the platform-level interrupt controller
  (PLIC).

  All RISC-V systems that conform to the supervisor ISA specification are
  required to have a HLIC with these three interrupt sources present.  Since
  the interrupt map is defined by the ISA it's not listed in the HLIC's device
  tree entry, though external interrupt controllers (like the PLIC, for
  example) will need to define how their interrupts map to the relevant HLICs.
  This means a PLIC interrupt property will typically list the HLICs for all
  present HARTs in the system.

maintainers:
  - Palmer Dabbelt <palmer@dabbelt.com>
  - Paul Walmsley <paul.walmsley@sifive.com>

properties:
  compatible:
    oneOf:
      - items:
          - const: andestech,cpu-intc
          - const: riscv,cpu-intc
      - const: riscv,cpu-intc

  interrupt-controller: true

  '#interrupt-cells':
    const: 1
    description: |
      The interrupt sources are defined by the RISC-V supervisor ISA manual,
      with only the following three interrupts being defined for
      supervisor mode:
        - Source 1 is the supervisor software interrupt, which can be sent by
          an SBI call and is reserved for use by software.
        - Source 5 is the supervisor timer interrupt, which can be configured
          by SBI calls and implements a one-shot timer.
        - Source 9 is the supervisor external interrupt, which chains to all
          other device interrupts.

required:
  - compatible
  - '#interrupt-cells'
  - interrupt-controller

additionalProperties: false

examples:
  - |
    interrupt-controller {
        #interrupt-cells = <1>;
        compatible = "riscv,cpu-intc";
        interrupt-controller;
    };
+1 −20
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@@ -103,26 +103,7 @@ properties:

  interrupt-controller:
    type: object
    additionalProperties: false
    description: Describes the CPU's local interrupt controller

    properties:
      '#interrupt-cells':
        const: 1

      compatible:
        oneOf:
          - items:
              - const: andestech,cpu-intc
              - const: riscv,cpu-intc
          - const: riscv,cpu-intc

      interrupt-controller: true

    required:
      - '#interrupt-cells'
      - compatible
      - interrupt-controller
    $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml#

  cpu-idle-states:
    $ref: /schemas/types.yaml#/definitions/phandle-array
+132 −0
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@@ -177,6 +177,13 @@ properties:
            is supported as ratified at commit 5059e0ca641c ("update to
            ratified") of the riscv-zacas.

        - const: zawrs
          description: |
            The Zawrs extension for entering a low-power state or for trapping
            to a hypervisor while waiting on a store to a memory location, as
            ratified in commit 98918c844281 ("Merge pull request #1217 from
            riscv/zawrs") of riscv-isa-manual.

        - const: zba
          description: |
            The standard Zba bit-manipulation extension for address generation
@@ -220,6 +227,43 @@ properties:
            instructions as ratified at commit 6d33919 ("Merge pull request #158
            from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.

        - const: zca
          description: |
            The Zca extension part of Zc* standard extensions for code size
            reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on
            RV64 as it contains no instructions") of riscv-code-size-reduction,
            merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
            of zc.adoc to src tree.").

        - const: zcb
          description: |
            The Zcb extension part of Zc* standard extensions for code size
            reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on
            RV64 as it contains no instructions") of riscv-code-size-reduction,
            merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
            of zc.adoc to src tree.").

        - const: zcd
          description: |
            The Zcd extension part of Zc* standard extensions for code size
            reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on
            RV64 as it contains no instructions") of riscv-code-size-reduction,
            merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
            of zc.adoc to src tree.").

        - const: zcf
          description: |
            The Zcf extension part of Zc* standard extensions for code size
            reduction, as ratified in commit 8be3419c1c0 ("Zcf doesn't exist on
            RV64 as it contains no instructions") of riscv-code-size-reduction,
            merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
            of zc.adoc to src tree.").

        - const: zcmop
          description:
            The standard Zcmop extension version 1.0, as ratified in commit
            c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual.

        - const: zfa
          description:
            The standard Zfa extension for additional floating point
@@ -363,6 +407,11 @@ properties:
            ratified in the 20191213 version of the unprivileged ISA
            specification.

        - const: zimop
          description:
            The standard Zimop extension version 1.0, as ratified in commit
            58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual.

        - const: ztso
          description:
            The standard Ztso extension for total store ordering, as ratified
@@ -381,6 +430,36 @@ properties:
            instructions, as ratified in commit 56ed795 ("Update
            riscv-crypto-spec-vector.adoc") of riscv-crypto.

        - const: zve32f
          description:
            The standard Zve32f extension for embedded processors, as ratified
            in commit 6f702a2 ("Vector extensions are now ratified") of
            riscv-v-spec.

        - const: zve32x
          description:
            The standard Zve32x extension for embedded processors, as ratified
            in commit 6f702a2 ("Vector extensions are now ratified") of
            riscv-v-spec.

        - const: zve64d
          description:
            The standard Zve64d extension for embedded processors, as ratified
            in commit 6f702a2 ("Vector extensions are now ratified") of
            riscv-v-spec.

        - const: zve64f
          description:
            The standard Zve64f extension for embedded processors, as ratified
            in commit 6f702a2 ("Vector extensions are now ratified") of
            riscv-v-spec.

        - const: zve64x
          description:
            The standard Zve64x extension for embedded processors, as ratified
            in commit 6f702a2 ("Vector extensions are now ratified") of
            riscv-v-spec.

        - const: zvfh
          description:
            The standard Zvfh extension for vectored half-precision
@@ -484,5 +563,58 @@ properties:
            Registers in the AX45MP datasheet.
            https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf

    allOf:
      # Zcb depends on Zca
      - if:
          contains:
            const: zcb
        then:
          contains:
            const: zca
      # Zcd depends on Zca and D
      - if:
          contains:
            const: zcd
        then:
          allOf:
            - contains:
                const: zca
            - contains:
                const: d
      # Zcf depends on Zca and F
      - if:
          contains:
            const: zcf
        then:
          allOf:
            - contains:
                const: zca
            - contains:
                const: f
      # Zcmop depends on Zca
      - if:
          contains:
            const: zcmop
        then:
          contains:
            const: zca

allOf:
  # Zcf extension does not exist on rv64
  - if:
      properties:
        riscv,isa-extensions:
          contains:
            const: zcf
        riscv,isa-base:
          contains:
            const: rv64i
    then:
      properties:
        riscv,isa-extensions:
          not:
            contains:
              const: zcf

additionalProperties: true
...
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