Commit f5a972df authored by Qili Lu's avatar Qili Lu Committed by Alex Deucher
Browse files

drm/amd/display: fix dccg root clock optimization related hang 



[Why]
enable dpp rcg before we disable dppclk in hw_init cause system
hang/reboot

[How]
we remove dccg rcg related code from init into a separate function and
call it after we init pipe

Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarQili Lu <qili.lu@amd.com>
Signed-off-by: default avatarHamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 5359d5bc

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

+9 −5
Original line number Diff line number Diff line
@@ -1748,10 +1748,6 @@ void dccg35_init(struct dccg *dccg) 
			dccg35_set_dpstreamclk_root_clock_gating(dccg, otg_inst, false);

		}



	if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp)

		for (otg_inst = 0; otg_inst < 4; otg_inst++)

			dccg35_set_dppclk_root_clock_gating(dccg, otg_inst, 0);



/*

	dccg35_enable_global_fgcg_rep(

		dccg, dccg->ctx->dc->debug.enable_fine_grain_clock_gating.bits
@@ -2336,6 +2332,14 @@ static void dccg35_disable_symclk_se_cb( 
	/* DMU PHY sequence switches SYMCLK_BE (link_enc_inst) to ref clock once PHY is turned off */

}



void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating)

{



	if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) {

		dccg35_set_dppclk_root_clock_gating(dccg, pipe_idx, disable_clock_gating);

	}

}



static const struct dccg_funcs dccg35_funcs_new = {

	.update_dpp_dto = dccg35_update_dpp_dto_cb,

	.dpp_root_clock_control = dccg35_dpp_root_clock_control_cb,
@@ -2396,7 +2400,7 @@ static const struct dccg_funcs dccg35_funcs = { 
	.enable_symclk_se = dccg35_enable_symclk_se,

	.disable_symclk_se = dccg35_disable_symclk_se,

	.set_dtbclk_p_src = dccg35_set_dtbclk_p_src,



	.dccg_root_gate_disable_control = dccg35_root_gate_disable_control,

};



struct dccg *dccg35_create(

drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h

+1 −0
Original line number Diff line number Diff line
@@ -241,6 +241,7 @@ struct dccg *dccg35_create( 
void dccg35_init(struct dccg *dccg);



void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value);

void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating);





#endif //__DCN35_DCCG_H__

drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c

+4 −0
Original line number Diff line number Diff line
@@ -240,6 +240,10 @@ void dcn35_init_hw(struct dc *dc) 
			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,

					!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);

	}

	if (res_pool->dccg->funcs->dccg_root_gate_disable_control) {

		for (i = 0; i < res_pool->pipe_count; i++)

			res_pool->dccg->funcs->dccg_root_gate_disable_control(res_pool->dccg, i, 0);

	}



	for (i = 0; i < res_pool->audio_count; i++) {

		struct audio *audio = res_pool->audios[i];

drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h

+1 −0
Original line number Diff line number Diff line
@@ -213,6 +213,7 @@ struct dccg_funcs { 
			uint32_t otg_inst);

	void (*set_dto_dscclk)(struct dccg *dccg, uint32_t dsc_inst);

	void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst);

	void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating);

};



#endif //__DAL_DCCG_H__